236 	const struct bxt_ddi_phy_info *phy_info, *phys;  in bxt_port_to_phy_channel()  local
242 		phy_info = &phys[i];  in bxt_port_to_phy_channel()
244 		if (port == phy_info->channel[DPIO_CH0].port) {  in bxt_port_to_phy_channel()
250 		if (phy_info->dual_channel &&  in bxt_port_to_phy_channel()
251 		    port == phy_info->channel[DPIO_CH1].port) {  in bxt_port_to_phy_channel()
309 	const struct bxt_ddi_phy_info *phy_info;  in bxt_ddi_phy_is_enabled()  local
311 	phy_info = bxt_get_phy_info(dev_priv, phy);  in bxt_ddi_phy_is_enabled()
313 	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))  in bxt_ddi_phy_is_enabled()
354 	const struct bxt_ddi_phy_info *phy_info;  in _bxt_ddi_phy_init()  local
357 	phy_info = bxt_get_phy_info(dev_priv, phy);  in _bxt_ddi_phy_init()
361 		if (phy_info->rcomp_phy != -1)  in _bxt_ddi_phy_init()
375 	val |= phy_info->pwron_mask;  in _bxt_ddi_phy_init()
409 	if (phy_info->dual_channel) {  in _bxt_ddi_phy_init()
415 	if (phy_info->rcomp_phy != -1) {  in _bxt_ddi_phy_init()
418 		bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);  in _bxt_ddi_phy_init()
426 							  phy_info->rcomp_phy);  in _bxt_ddi_phy_init()
437 	if (phy_info->reset_delay)  in _bxt_ddi_phy_init()
438 		udelay(phy_info->reset_delay);  in _bxt_ddi_phy_init()
447 	const struct bxt_ddi_phy_info *phy_info;  in bxt_ddi_phy_uninit()  local
450 	phy_info = bxt_get_phy_info(dev_priv, phy);  in bxt_ddi_phy_uninit()
457 	val &= ~phy_info->pwron_mask;  in bxt_ddi_phy_uninit()
463 	const struct bxt_ddi_phy_info *phy_info =  in bxt_ddi_phy_init()  local
465 	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;  in bxt_ddi_phy_init()
517 	const struct bxt_ddi_phy_info *phy_info;  in bxt_ddi_phy_verify_state()  local
521 	phy_info = bxt_get_phy_info(dev_priv, phy);  in bxt_ddi_phy_verify_state()
545 	if (phy_info->dual_channel)  in bxt_ddi_phy_verify_state()
550 	if (phy_info->rcomp_phy != -1) {  in bxt_ddi_phy_verify_state()