3440 	uint32_t	signal_levels = 0;  in g4x_signal_levels()  local
3445 		signal_levels |= DP_VOLTAGE_0_4;  in g4x_signal_levels()
3448 		signal_levels |= DP_VOLTAGE_0_6;  in g4x_signal_levels()
3451 		signal_levels |= DP_VOLTAGE_0_8;  in g4x_signal_levels()
3454 		signal_levels |= DP_VOLTAGE_1_2;  in g4x_signal_levels()
3460 		signal_levels |= DP_PRE_EMPHASIS_0;  in g4x_signal_levels()
3463 		signal_levels |= DP_PRE_EMPHASIS_3_5;  in g4x_signal_levels()
3466 		signal_levels |= DP_PRE_EMPHASIS_6;  in g4x_signal_levels()
3469 		signal_levels |= DP_PRE_EMPHASIS_9_5;  in g4x_signal_levels()
3472 	return signal_levels;  in g4x_signal_levels()
3479 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in snb_cpu_edp_signal_levels()  local
3481 	switch (signal_levels) {  in snb_cpu_edp_signal_levels()
3498 			      "0x%x\n", signal_levels);  in snb_cpu_edp_signal_levels()
3507 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in ivb_cpu_edp_signal_levels()  local
3509 	switch (signal_levels) {  in ivb_cpu_edp_signal_levels()
3529 			      "0x%x\n", signal_levels);  in ivb_cpu_edp_signal_levels()
3540 	uint32_t signal_levels, mask = 0;  in intel_dp_set_signal_levels()  local
3544 		signal_levels = bxt_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3546 		signal_levels = ddi_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3549 		signal_levels = chv_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3551 		signal_levels = vlv_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3553 		signal_levels = ivb_cpu_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3556 		signal_levels = snb_cpu_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3559 		signal_levels = g4x_signal_levels(train_set);  in intel_dp_set_signal_levels()
3564 		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);  in intel_dp_set_signal_levels()
3572 	intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;  in intel_dp_set_signal_levels()