782 	if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&  in intel_power_sequencer_reset()
829 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_pps_get_registers()
875 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in edp_notify_handler()
902 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in edp_have_panel_power()
915 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in edp_have_panel_vdd()
1567 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_set_clock()
2984 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_enable_dp()
2995 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_enable_dp()
3212 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_voltage_max()
3231 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_pre_emphasis_max()
3550 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_set_signal_levels()
3690 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_link_down()
5228 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_encoder_reset()
5601 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_init_panel_power_sequencer_registers()
5643 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_pps_init()
5730 			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_set_drrs_state()
5735 			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_set_drrs_state()
6105 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_edp_init_connector()
6208 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_init_connector()
6220 	if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in intel_dp_init_connector()
6325 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_init()