1436 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));  in _chv_enable_pll()
1628 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));  in chv_disable_pll()
6776 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));  in vlv_pllb_recal_opamp()
6781 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);  in vlv_pllb_recal_opamp()
6786 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));  in vlv_pllb_recal_opamp()
6790 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);  in vlv_pllb_recal_opamp()
6937 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));  in vlv_prepare_pll()
6989 	coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));  in vlv_prepare_pll()
7050 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_prepare_pll()
7058 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));  in chv_prepare_pll()
7091 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));  in chv_prepare_pll()
7098 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |  in chv_prepare_pll()
7704 	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));  in vlv_crtc_clock_get()
7808 	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));  in chv_crtc_clock_get()
7809 	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));  in chv_crtc_clock_get()
7810 	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));  in chv_crtc_clock_get()
7811 	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));  in chv_crtc_clock_get()
7812 	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_crtc_clock_get()