135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
137 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
143 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
145 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
152 static void vlv_prepare_pll(struct intel_crtc *crtc,
154 static void chv_prepare_pll(struct intel_crtc *crtc,
158 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
160 static void skylake_pfit_enable(struct intel_crtc *crtc);
161 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
162 static void ironlake_pfit_enable(struct intel_crtc *crtc);
895 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in vlv_find_best_dpll()
955 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in chv_find_best_dpll()
1017 bool intel_crtc_active(struct intel_crtc *crtc)  in intel_crtc_active()
1039 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in intel_pipe_to_cpu_transcoder()
1063 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)  in wait_for_pipe_scanline_moving()
1074 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)  in intel_wait_for_pipe_scanline_stopped()
1079 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)  in intel_wait_for_pipe_scanline_moving()
1087 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);  in intel_wait_for_pipe_off()
1300 static void assert_planes_disabled(struct intel_crtc *crtc)  in assert_planes_disabled()
1388 static void _vlv_enable_pll(struct intel_crtc *crtc,  in _vlv_enable_pll()
1406 static void vlv_enable_pll(struct intel_crtc *crtc,  in vlv_enable_pll()
1425 static void _chv_enable_pll(struct intel_crtc *crtc,  in _chv_enable_pll()
1457 static void chv_enable_pll(struct intel_crtc *crtc,  in chv_enable_pll()
1496 	struct intel_crtc *crtc;  in intel_num_dvo_pipes()
1507 static void i9xx_enable_pll(struct intel_crtc *crtc,  in i9xx_enable_pll()
1567 static void i9xx_disable_pll(struct intel_crtc *crtc)  in i9xx_disable_pll()
1671 	struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,  in ironlake_enable_pch_transcoder()  local
1677 	assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);  in ironlake_enable_pch_transcoder()
1703 		if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))  in ironlake_enable_pch_transcoder()
1712 		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))  in ironlake_enable_pch_transcoder()
1809 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)  in intel_crtc_pch_transcoder()
1821 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);  in intel_enable_pipe()
1877 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);  in intel_disable_pipe()
2692 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,  in intel_alloc_initial_plane_obj()
2771 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,  in intel_plane_disable_noatomic()
2789 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,  in intel_find_initial_plane_obj()  argument
2792 	struct drm_device *dev = intel_crtc->base.dev;  in intel_find_initial_plane_obj()
2796 	struct drm_plane *primary = intel_crtc->base.primary;  in intel_find_initial_plane_obj()
2798 	struct drm_crtc_state *crtc_state = intel_crtc->base.state;  in intel_find_initial_plane_obj()
2807 	if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {  in intel_find_initial_plane_obj()
2821 		if (c == &intel_crtc->base)  in intel_find_initial_plane_obj()
2845 	intel_plane_disable_noatomic(intel_crtc, intel_plane);  in intel_find_initial_plane_obj()
2859 			  intel_crtc->pipe, PTR_ERR(intel_state->vma));  in intel_find_initial_plane_obj()
2886 	plane_state->crtc = &intel_crtc->base;  in intel_find_initial_plane_obj()
3216 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in i9xx_plane_ctl()
3375 			       struct intel_crtc *crtc)  in i9xx_disable_plane()
3435 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)  in skl_detach_scaler()  argument
3437 	struct drm_device *dev = intel_crtc->base.dev;  in skl_detach_scaler()
3440 	I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);  in skl_detach_scaler()
3441 	I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);  in skl_detach_scaler()
3442 	I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);  in skl_detach_scaler()
3448 static void skl_detach_scalers(struct intel_crtc *intel_crtc)  in skl_detach_scalers()  argument
3453 	scaler_state = &intel_crtc->config->scaler_state;  in skl_detach_scalers()
3456 	for (i = 0; i < intel_crtc->num_scalers; i++) {  in skl_detach_scalers()
3458 			skl_detach_scaler(intel_crtc, i);  in skl_detach_scalers()
3832 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);  in intel_update_pipe_config()
3865 static void intel_fdi_normal_train(struct intel_crtc *crtc)  in intel_fdi_normal_train()
3907 static void ironlake_fdi_link_train(struct intel_crtc *crtc,  in ironlake_fdi_link_train()
4008 static void gen6_fdi_link_train(struct intel_crtc *crtc,  in gen6_fdi_link_train()
4141 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,  in ivb_manual_fdi_link_train()
4260 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)  in ironlake_fdi_pll_enable()  argument
4262 	struct drm_device *dev = intel_crtc->base.dev;  in ironlake_fdi_pll_enable()
4264 	int pipe = intel_crtc->pipe;  in ironlake_fdi_pll_enable()
4272 	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);  in ironlake_fdi_pll_enable()
4297 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)  in ironlake_fdi_pll_disable()  argument
4299 	struct drm_device *dev = intel_crtc->base.dev;  in ironlake_fdi_pll_disable()
4301 	int pipe = intel_crtc->pipe;  in ironlake_fdi_pll_disable()
4331 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ironlake_fdi_disable()  local
4332 	int pipe = intel_crtc->pipe;  in ironlake_fdi_disable()
4421 static void lpt_program_iclkip(struct intel_crtc *crtc)  in lpt_program_iclkip()
4535 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,  in ironlake_pch_transcoder_set_timings()
4580 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)  in ivybridge_update_fdi_bc_bifurcation()  argument
4582 	struct drm_device *dev = intel_crtc->base.dev;  in ivybridge_update_fdi_bc_bifurcation()
4584 	switch (intel_crtc->pipe) {  in ivybridge_update_fdi_bc_bifurcation()
4588 		if (intel_crtc->config->fdi_lanes > 2)  in ivybridge_update_fdi_bc_bifurcation()
4611 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in intel_get_crtc_new_encoder()
4643 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in ironlake_pch_enable()
4727 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in lpt_pch_enable()
4797 	struct intel_crtc *intel_crtc =  in skl_update_scaler()  local
4799 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);  in skl_update_scaler()
4847 				intel_crtc->pipe, scaler_user, *scaler_id,  in skl_update_scaler()
4871 			intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);  in skl_update_scaler()
4879 		intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,  in skl_update_scaler()
4970 static void skylake_scaler_disable(struct intel_crtc *crtc)  in skylake_scaler_disable()
4978 static void skylake_pfit_enable(struct intel_crtc *crtc)  in skylake_pfit_enable()
5008 static void ironlake_pfit_enable(struct intel_crtc *crtc)  in ironlake_pfit_enable()
5031 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in hsw_enable_ips()
5071 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in hsw_disable_ips()
5100 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)  in intel_crtc_dpms_overlay_disable()  argument
5102 	if (intel_crtc->overlay) {  in intel_crtc_dpms_overlay_disable()
5103 		struct drm_device *dev = intel_crtc->base.dev;  in intel_crtc_dpms_overlay_disable()
5106 		(void) intel_overlay_switch_off(intel_crtc->overlay);  in intel_crtc_dpms_overlay_disable()
5132 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_post_enable_primary()  local
5133 	int pipe = intel_crtc->pipe;  in intel_post_enable_primary()
5156 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_pre_disable_primary_noatomic()  local
5157 	int pipe = intel_crtc->pipe;  in intel_pre_disable_primary_noatomic()
5232 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);  in intel_post_plane_update()
5274 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);  in intel_pre_plane_update()
5364 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_crtc_disable_planes()  local
5366 	int pipe = intel_crtc->pipe;  in intel_crtc_disable_planes()
5368 	intel_crtc_dpms_overlay_disable(intel_crtc);  in intel_crtc_disable_planes()
5371 		to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);  in intel_crtc_disable_planes()
5507 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ironlake_crtc_enable()  local
5508 	int pipe = intel_crtc->pipe;  in ironlake_crtc_enable()
5512 	if (WARN_ON(intel_crtc->active))  in ironlake_crtc_enable()
5528 	if (intel_crtc->config->has_pch_encoder)  in ironlake_crtc_enable()
5529 		intel_prepare_shared_dpll(intel_crtc);  in ironlake_crtc_enable()
5531 	if (intel_crtc_has_dp_encoder(intel_crtc->config))  in ironlake_crtc_enable()
5532 		intel_dp_set_m_n(intel_crtc, M1_N1);  in ironlake_crtc_enable()
5534 	intel_set_pipe_timings(intel_crtc);  in ironlake_crtc_enable()
5535 	intel_set_pipe_src_size(intel_crtc);  in ironlake_crtc_enable()
5537 	if (intel_crtc->config->has_pch_encoder) {  in ironlake_crtc_enable()
5538 		intel_cpu_transcoder_set_m_n(intel_crtc,  in ironlake_crtc_enable()
5539 				     &intel_crtc->config->fdi_m_n, NULL);  in ironlake_crtc_enable()
5544 	intel_crtc->active = true;  in ironlake_crtc_enable()
5548 	if (intel_crtc->config->has_pch_encoder) {  in ironlake_crtc_enable()
5552 		ironlake_fdi_pll_enable(intel_crtc);  in ironlake_crtc_enable()
5558 	ironlake_pfit_enable(intel_crtc);  in ironlake_crtc_enable()
5567 		dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);  in ironlake_crtc_enable()
5570 	if (intel_crtc->config->has_pch_encoder)  in ironlake_crtc_enable()
5579 		cpt_verify_modeset(dev, intel_crtc->pipe);  in ironlake_crtc_enable()
5587 	if (intel_crtc->config->has_pch_encoder) {  in ironlake_crtc_enable()
5596 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)  in hsw_crtc_supports_ips()
5615 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)  in icl_pipe_mbus_enable()
5634 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in haswell_crtc_enable()  local
5635 	int pipe = intel_crtc->pipe, hsw_workaround_pipe;  in haswell_crtc_enable()
5636 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;  in haswell_crtc_enable()
5642 	if (WARN_ON(intel_crtc->active))  in haswell_crtc_enable()
5647 	if (intel_crtc->config->shared_dpll)  in haswell_crtc_enable()
5648 		intel_enable_shared_dpll(intel_crtc);  in haswell_crtc_enable()
5655 	if (intel_crtc_has_dp_encoder(intel_crtc->config))  in haswell_crtc_enable()
5656 		intel_dp_set_m_n(intel_crtc, M1_N1);  in haswell_crtc_enable()
5659 		intel_set_pipe_timings(intel_crtc);  in haswell_crtc_enable()
5661 	intel_set_pipe_src_size(intel_crtc);  in haswell_crtc_enable()
5666 			   intel_crtc->config->pixel_multiplier - 1);  in haswell_crtc_enable()
5669 	if (intel_crtc->config->has_pch_encoder) {  in haswell_crtc_enable()
5670 		intel_cpu_transcoder_set_m_n(intel_crtc,  in haswell_crtc_enable()
5671 				     &intel_crtc->config->fdi_m_n, NULL);  in haswell_crtc_enable()
5681 	intel_crtc->active = true;  in haswell_crtc_enable()
5685 			 intel_crtc->config->pch_pfit.enabled;  in haswell_crtc_enable()
5690 		skylake_pfit_enable(intel_crtc);  in haswell_crtc_enable()
5692 		ironlake_pfit_enable(intel_crtc);  in haswell_crtc_enable()
5719 		icl_pipe_mbus_enable(intel_crtc);  in haswell_crtc_enable()
5725 	if (intel_crtc->config->has_pch_encoder)  in haswell_crtc_enable()
5728 	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))  in haswell_crtc_enable()
5750 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)  in ironlake_pfit_disable()
5771 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ironlake_crtc_disable()  local
5772 	int pipe = intel_crtc->pipe;  in ironlake_crtc_disable()
5789 	ironlake_pfit_disable(intel_crtc, false);  in ironlake_crtc_disable()
5791 	if (intel_crtc->config->has_pch_encoder)  in ironlake_crtc_disable()
5796 	if (intel_crtc->config->has_pch_encoder) {  in ironlake_crtc_disable()
5817 		ironlake_fdi_pll_disable(intel_crtc);  in ironlake_crtc_disable()
5829 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in haswell_crtc_disable()  local
5848 		skylake_scaler_disable(intel_crtc);  in haswell_crtc_disable()
5850 		ironlake_pfit_disable(intel_crtc, false);  in haswell_crtc_disable()
5858 static void i9xx_pfit_enable(struct intel_crtc *crtc)  in i9xx_pfit_enable()
5925 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in get_crtc_power_domains()  local
5926 	enum pipe pipe = intel_crtc->pipe;  in get_crtc_power_domains()
5959 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in modeset_get_crtc_power_domains()  local
5963 	old_domains = intel_crtc->enabled_power_domains;  in modeset_get_crtc_power_domains()
5964 	intel_crtc->enabled_power_domains = new_domains =  in modeset_get_crtc_power_domains()
5992 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in valleyview_crtc_enable()  local
5993 	int pipe = intel_crtc->pipe;  in valleyview_crtc_enable()
5995 	if (WARN_ON(intel_crtc->active))  in valleyview_crtc_enable()
5998 	if (intel_crtc_has_dp_encoder(intel_crtc->config))  in valleyview_crtc_enable()
5999 		intel_dp_set_m_n(intel_crtc, M1_N1);  in valleyview_crtc_enable()
6001 	intel_set_pipe_timings(intel_crtc);  in valleyview_crtc_enable()
6002 	intel_set_pipe_src_size(intel_crtc);  in valleyview_crtc_enable()
6011 	i9xx_set_pipeconf(intel_crtc);  in valleyview_crtc_enable()
6013 	intel_crtc->active = true;  in valleyview_crtc_enable()
6020 		chv_prepare_pll(intel_crtc, intel_crtc->config);  in valleyview_crtc_enable()
6021 		chv_enable_pll(intel_crtc, intel_crtc->config);  in valleyview_crtc_enable()
6023 		vlv_prepare_pll(intel_crtc, intel_crtc->config);  in valleyview_crtc_enable()
6024 		vlv_enable_pll(intel_crtc, intel_crtc->config);  in valleyview_crtc_enable()
6029 	i9xx_pfit_enable(intel_crtc);  in valleyview_crtc_enable()
6043 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)  in i9xx_set_pll_dividers()
6060 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in i9xx_crtc_enable()  local
6061 	enum pipe pipe = intel_crtc->pipe;  in i9xx_crtc_enable()
6063 	if (WARN_ON(intel_crtc->active))  in i9xx_crtc_enable()
6066 	i9xx_set_pll_dividers(intel_crtc);  in i9xx_crtc_enable()
6068 	if (intel_crtc_has_dp_encoder(intel_crtc->config))  in i9xx_crtc_enable()
6069 		intel_dp_set_m_n(intel_crtc, M1_N1);  in i9xx_crtc_enable()
6071 	intel_set_pipe_timings(intel_crtc);  in i9xx_crtc_enable()
6072 	intel_set_pipe_src_size(intel_crtc);  in i9xx_crtc_enable()
6074 	i9xx_set_pipeconf(intel_crtc);  in i9xx_crtc_enable()
6076 	intel_crtc->active = true;  in i9xx_crtc_enable()
6083 	i9xx_enable_pll(intel_crtc, pipe_config);  in i9xx_crtc_enable()
6085 	i9xx_pfit_enable(intel_crtc);  in i9xx_crtc_enable()
6091 						     intel_crtc->config);  in i9xx_crtc_enable()
6093 		intel_update_watermarks(intel_crtc);  in i9xx_crtc_enable()
6102 static void i9xx_pfit_disable(struct intel_crtc *crtc)  in i9xx_pfit_disable()
6123 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in i9xx_crtc_disable()  local
6124 	int pipe = intel_crtc->pipe;  in i9xx_crtc_disable()
6140 	i9xx_pfit_disable(intel_crtc);  in i9xx_crtc_disable()
6144 	if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {  in i9xx_crtc_disable()
6150 			i9xx_disable_pll(intel_crtc);  in i9xx_crtc_disable()
6159 		intel_update_watermarks(intel_crtc);  in i9xx_crtc_disable()
6170 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_crtc_disable_noatomic()  local
6179 	if (!intel_crtc->active)  in intel_crtc_disable_noatomic()
6182 	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {  in intel_crtc_disable_noatomic()
6187 			intel_plane_disable_noatomic(intel_crtc, plane);  in intel_crtc_disable_noatomic()
6200 	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);  in intel_crtc_disable_noatomic()
6214 	intel_crtc->active = false;  in intel_crtc_disable_noatomic()
6222 	intel_fbc_disable(intel_crtc);  in intel_crtc_disable_noatomic()
6223 	intel_update_watermarks(intel_crtc);  in intel_crtc_disable_noatomic()
6224 	intel_disable_shared_dpll(intel_crtc);  in intel_crtc_disable_noatomic()
6226 	domains = intel_crtc->enabled_power_domains;  in intel_crtc_disable_noatomic()
6229 	intel_crtc->enabled_power_domains = 0;  in intel_crtc_disable_noatomic()
6231 	dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);  in intel_crtc_disable_noatomic()
6232 	dev_priv->min_cdclk[intel_crtc->pipe] = 0;  in intel_crtc_disable_noatomic()
6233 	dev_priv->min_voltage_level[intel_crtc->pipe] = 0;  in intel_crtc_disable_noatomic()
6375 	struct intel_crtc *other_crtc;  in ironlake_check_fdi_lanes()
6443 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,  in ironlake_fdi_compute_config()  argument
6446 	struct drm_device *dev = intel_crtc->base.dev;  in ironlake_fdi_compute_config()
6471 	ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);  in ironlake_fdi_compute_config()
6490 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in hsw_crtc_state_ips_capable()
6542 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)  in intel_crtc_supports_double_wide()
6599 static int intel_crtc_compute_config(struct intel_crtc *crtc,  in intel_crtc_compute_config()
6740 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,  in i9xx_update_pll_dividers()
6796 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,  in intel_pch_transcoder_set_m_n()
6809 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,  in intel_cpu_transcoder_set_m_n()
6842 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)  in intel_dp_set_m_n()
6867 static void vlv_compute_dpll(struct intel_crtc *crtc,  in vlv_compute_dpll()
6884 static void chv_compute_dpll(struct intel_crtc *crtc,  in chv_compute_dpll()
6900 static void vlv_prepare_pll(struct intel_crtc *crtc,  in vlv_prepare_pll()
6999 static void chv_prepare_pll(struct intel_crtc *crtc,  in chv_prepare_pll()
7117 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in vlv_force_pll_on()
7159 static void i9xx_compute_dpll(struct intel_crtc *crtc,  in i9xx_compute_dpll()
7232 static void i8xx_compute_dpll(struct intel_crtc *crtc,  in i8xx_compute_dpll()
7270 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)  in intel_set_pipe_timings()  argument
7272 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);  in intel_set_pipe_timings()
7273 	enum pipe pipe = intel_crtc->pipe;  in intel_set_pipe_timings()
7274 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;  in intel_set_pipe_timings()
7275 	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;  in intel_set_pipe_timings()
7289 		if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))  in intel_set_pipe_timings()
7331 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)  in intel_set_pipe_src_size()  argument
7333 	struct drm_device *dev = intel_crtc->base.dev;  in intel_set_pipe_src_size()
7335 	enum pipe pipe = intel_crtc->pipe;  in intel_set_pipe_src_size()
7341 		   ((intel_crtc->config->pipe_src_w - 1) << 16) |  in intel_set_pipe_src_size()
7342 		   (intel_crtc->config->pipe_src_h - 1));  in intel_set_pipe_src_size()
7345 static void intel_get_pipe_timings(struct intel_crtc *crtc,  in intel_get_pipe_timings()
7380 static void intel_get_pipe_src_size(struct intel_crtc *crtc,  in intel_get_pipe_src_size()
7418 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)  in i9xx_set_pipeconf()  argument
7420 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);  in i9xx_set_pipeconf()
7427 		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;  in i9xx_set_pipeconf()
7429 	if (intel_crtc->config->double_wide)  in i9xx_set_pipeconf()
7436 		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)  in i9xx_set_pipeconf()
7440 		switch (intel_crtc->config->pipe_bpp) {  in i9xx_set_pipeconf()
7456 	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
7458 		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))  in i9xx_set_pipeconf()
7466 	     intel_crtc->config->limited_color_range)  in i9xx_set_pipeconf()
7469 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
7470 	POSTING_READ(PIPECONF(intel_crtc->pipe));  in i9xx_set_pipeconf()
7473 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,  in i8xx_crtc_compute_clock()
7509 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,  in g4x_crtc_compute_clock()
7552 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,  in pnv_crtc_compute_clock()
7586 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,  in i9xx_crtc_compute_clock()
7620 static int chv_crtc_compute_clock(struct intel_crtc *crtc,  in chv_crtc_compute_clock()
7641 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,  in vlv_crtc_compute_clock()
7662 static void i9xx_get_pfit_config(struct intel_crtc *crtc,  in i9xx_get_pfit_config()
7689 static void vlv_crtc_clock_get(struct intel_crtc *crtc,  in vlv_crtc_clock_get()
7717 i9xx_get_initial_plane_config(struct intel_crtc *crtc,  in i9xx_get_initial_plane_config()
7792 static void chv_crtc_clock_get(struct intel_crtc *crtc,  in chv_crtc_clock_get()
7826 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,  in i9xx_get_pipe_config()
8372 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ironlake_set_pipeconf()  local
8373 	int pipe = intel_crtc->pipe;  in ironlake_set_pipeconf()
8378 	switch (intel_crtc->config->pipe_bpp) {  in ironlake_set_pipeconf()
8396 	if (intel_crtc->config->dither)  in ironlake_set_pipeconf()
8399 	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ironlake_set_pipeconf()
8404 	if (intel_crtc->config->limited_color_range)  in ironlake_set_pipeconf()
8414 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in haswell_set_pipeconf()  local
8415 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;  in haswell_set_pipeconf()
8418 	if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)  in haswell_set_pipeconf()
8421 	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in haswell_set_pipeconf()
8433 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in haswell_set_pipemisc()  local
8434 	struct intel_crtc_state *config = intel_crtc->config;  in haswell_set_pipemisc()
8439 		switch (intel_crtc->config->pipe_bpp) {  in haswell_set_pipemisc()
8457 		if (intel_crtc->config->dither)  in haswell_set_pipemisc()
8466 		I915_WRITE(PIPEMISC(intel_crtc->pipe), val);  in haswell_set_pipemisc()
8486 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,  in ironlake_compute_dpll()  argument
8490 	struct drm_crtc *crtc = &intel_crtc->base;  in ironlake_compute_dpll()
8588 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,  in ironlake_crtc_compute_clock()
8643 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,  in intel_pch_transcoder_get_m_n()
8659 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,  in intel_cpu_transcoder_get_m_n()
8700 void intel_dp_get_m_n(struct intel_crtc *crtc,  in intel_dp_get_m_n()
8711 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,  in ironlake_get_fdi_m_n_config()
8718 static void skylake_get_pfit_config(struct intel_crtc *crtc,  in skylake_get_pfit_config()
8749 skylake_get_initial_plane_config(struct intel_crtc *crtc,  in skylake_get_initial_plane_config()
8851 static void ironlake_get_pfit_config(struct intel_crtc *crtc,  in ironlake_get_pfit_config()
8875 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,  in ironlake_get_pipe_config()
8975 	struct intel_crtc *crtc;  in assert_can_disable_lcpll()
9192 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,  in haswell_crtc_compute_clock()
9342 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,  in hsw_get_transcoder_state()
9394 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,  in bxt_get_dsi_transcoder_state()
9442 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,  in haswell_get_ddi_port_state()
9488 static bool haswell_get_pipe_config(struct intel_crtc *crtc,  in haswell_get_pipe_config()
9784 				struct intel_crtc *crtc)  in i845_disable_cursor()
9814 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);  in i9xx_cursor_ctl()
10003 				struct intel_crtc *crtc)  in i9xx_disable_cursor()
10098 	struct intel_crtc *intel_crtc;  in intel_get_load_detect_pipe()  local
10171 	intel_crtc = to_intel_crtc(crtc);  in intel_get_load_detect_pipe()
10193 	crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);  in intel_get_load_detect_pipe()
10232 	intel_wait_for_vblank(dev_priv, intel_crtc->pipe);  in intel_get_load_detect_pipe()
10291 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,  in i9xx_crtc_clock_get()
10399 static void ironlake_pch_clock_get(struct intel_crtc *crtc,  in ironlake_pch_clock_get()
10424 	struct intel_crtc *crtc;  in intel_encoder_current_mode()
10461 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_crtc_destroy()  local
10464 	kfree(intel_crtc);  in intel_crtc_destroy()
10518 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_plane_atomic_calc_changes()  local
10568 			 intel_crtc->base.base.id, intel_crtc->base.name,  in intel_plane_atomic_calc_changes()
10625 					 struct intel_crtc *crtc,  in check_single_encoder_cloning()
10651 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_crtc_atomic_check()  local
10664 		ret = dev_priv->display.crtc_compute_clock(intel_crtc,  in intel_crtc_atomic_check()
10702 								intel_crtc,  in intel_crtc_atomic_check()
10718 			ret = skl_check_pipe_max_pixel_rate(intel_crtc,  in intel_crtc_atomic_check()
10721 			ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,  in intel_crtc_atomic_check()
10789 compute_baseline_pipe_bpp(struct intel_crtc *crtc,  in compute_baseline_pipe_bpp()
10890 static void intel_dump_pipe_config(struct intel_crtc *crtc,  in intel_dump_pipe_config()
11628 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in verify_wm_state()  local
11629 	const enum pipe pipe = intel_crtc->pipe;  in verify_wm_state()
11825 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in verify_crtc_state()  local
11839 	active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);  in verify_crtc_state()
11849 	I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,  in verify_crtc_state()
11851 	     "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);  in verify_crtc_state()
11861 		I915_STATE_WARN(active && intel_crtc->pipe != pipe,  in verify_crtc_state()
11880 		intel_dump_pipe_config(intel_crtc, pipe_config,  in verify_crtc_state()
11882 		intel_dump_pipe_config(intel_crtc, sw_config,  in verify_crtc_state()
12015 static void update_scanline_offset(struct intel_crtc *crtc)  in update_scanline_offset()
12074 		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_modeset_clear_plls()  local
12086 		intel_release_shared_dpll(old_dpll, intel_crtc, state);  in intel_modeset_clear_plls()
12099 	struct intel_crtc *intel_crtc;  in haswell_mode_set_planes_workaround()  local
12108 		intel_crtc = to_intel_crtc(crtc);  in haswell_mode_set_planes_workaround()
12118 			first_pipe = intel_crtc->pipe;  in haswell_mode_set_planes_workaround()
12127 	for_each_intel_crtc(state->dev, intel_crtc) {  in haswell_mode_set_planes_workaround()
12130 		pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);  in haswell_mode_set_planes_workaround()
12144 		enabled_pipe = intel_crtc->pipe;  in haswell_mode_set_planes_workaround()
12384 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)  in intel_crtc_get_vblank_counter()
12401 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_update_crtc()  local
12409 		update_scanline_offset(intel_crtc);  in intel_update_crtc()
12413 		intel_crtc_enable_pipe_crc(intel_crtc);  in intel_update_crtc()
12420 		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);  in intel_update_crtc()
12445 	struct intel_crtc *intel_crtc;  in skl_update_crtcs()  local
12479 			intel_crtc = to_intel_crtc(crtc);  in skl_update_crtcs()
12481 			pipe = intel_crtc->pipe;  in skl_update_crtcs()
12596 		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_atomic_commit_tail()  local
12619 			intel_crtc_disable_pipe_crc(intel_crtc);  in intel_atomic_commit_tail()
12622 			intel_crtc->active = false;  in intel_atomic_commit_tail()
12623 			intel_fbc_disable(intel_crtc);  in intel_atomic_commit_tail()
12624 			intel_disable_shared_dpll(intel_crtc);  in intel_atomic_commit_tail()
12837 		struct intel_crtc *crtc;  in intel_atomic_commit()
13157 skl_max_scale(struct intel_crtc *intel_crtc,  in skl_max_scale()  argument
13165 	if (!intel_crtc || !crtc_state->base.enable)  in skl_max_scale()
13168 	dev_priv = to_i915(intel_crtc->base.dev);  in skl_max_scale()
13253 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_begin_crtc_commit()  local
13259 		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);  in intel_begin_crtc_commit()
13278 		skl_detach_scalers(intel_crtc);  in intel_begin_crtc_commit()
13286 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,  in intel_crtc_arm_fifo_underrun()
13305 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_finish_crtc_commit()  local
13309 		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);  in intel_finish_crtc_commit()
13316 		intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);  in intel_finish_crtc_commit()
13897 static void intel_crtc_init_scalers(struct intel_crtc *crtc,  in intel_crtc_init_scalers()
13921 	struct intel_crtc *intel_crtc;  in intel_crtc_init()  local
13927 	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);  in intel_crtc_init()
13928 	if (!intel_crtc)  in intel_crtc_init()
13936 	intel_crtc->config = crtc_state;  in intel_crtc_init()
13937 	intel_crtc->base.state = &crtc_state->base;  in intel_crtc_init()
13938 	crtc_state->base.crtc = &intel_crtc->base;  in intel_crtc_init()
13945 	intel_crtc->plane_ids_mask |= BIT(primary->id);  in intel_crtc_init()
13955 		intel_crtc->plane_ids_mask |= BIT(plane->id);  in intel_crtc_init()
13963 	intel_crtc->plane_ids_mask |= BIT(cursor->id);  in intel_crtc_init()
13965 	ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,  in intel_crtc_init()
13972 	intel_crtc->pipe = pipe;  in intel_crtc_init()
13975 	intel_crtc_init_scalers(intel_crtc, crtc_state);  in intel_crtc_init()
13979 	dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;  in intel_crtc_init()
13986 		dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;  in intel_crtc_init()
13989 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);  in intel_crtc_init()
13991 	intel_color_init(&intel_crtc->base);  in intel_crtc_init()
13993 	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);  in intel_crtc_init()
14003 	kfree(intel_crtc);  in intel_crtc_init()
14025 	struct intel_crtc *crtc;  in intel_get_pipe_from_crtc_id_ioctl()
15141 	struct intel_crtc *crtc;  in intel_modeset_init()
15278 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in i830_enable_pipe()
15348 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in i830_disable_pipe()
15368 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,  in intel_plane_mapping_ok()
15382 	struct intel_crtc *crtc;  in intel_sanitize_plane_mapping()
15400 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)  in intel_crtc_has_encoders()
15429 static void intel_sanitize_crtc(struct intel_crtc *crtc,  in intel_sanitize_crtc()
15568 static void readout_plane_state(struct intel_crtc *crtc)  in readout_plane_state()
15591 	struct intel_crtc *crtc;  in intel_modeset_readout_hw_state()
15793 	struct intel_crtc *crtc;  in intel_modeset_setup_hw_state()