Lines Matching refs:dpll_hw_state
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1420 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1481 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1489 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1512 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll()
1549 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
6048 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
6049 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
6757 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
6761 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
6763 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
6870 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
6873 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
6877 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
6880 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
6887 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
6890 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
6894 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
6896 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
6912 pipe_config->dpll_hw_state.dpll & in vlv_prepare_pll()
6916 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
7013 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7016 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
7223 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
7228 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
7267 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
7481 memset(&crtc_state->dpll_hw_state, 0, in i8xx_crtc_compute_clock()
7482 sizeof(crtc_state->dpll_hw_state)); in i8xx_crtc_compute_clock()
7517 memset(&crtc_state->dpll_hw_state, 0, in g4x_crtc_compute_clock()
7518 sizeof(crtc_state->dpll_hw_state)); in g4x_crtc_compute_clock()
7560 memset(&crtc_state->dpll_hw_state, 0, in pnv_crtc_compute_clock()
7561 sizeof(crtc_state->dpll_hw_state)); in pnv_crtc_compute_clock()
7594 memset(&crtc_state->dpll_hw_state, 0, in i9xx_crtc_compute_clock()
7595 sizeof(crtc_state->dpll_hw_state)); in i9xx_crtc_compute_clock()
7626 memset(&crtc_state->dpll_hw_state, 0, in chv_crtc_compute_clock()
7627 sizeof(crtc_state->dpll_hw_state)); in chv_crtc_compute_clock()
7647 memset(&crtc_state->dpll_hw_state, 0, in vlv_crtc_compute_clock()
7648 sizeof(crtc_state->dpll_hw_state)); in vlv_crtc_compute_clock()
7700 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
7804 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
7885 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
7898 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7906 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
7908 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7909 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7912 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
8583 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_compute_dpll()
8584 crtc_state->dpll_hw_state.fp0 = fp; in ironlake_compute_dpll()
8585 crtc_state->dpll_hw_state.fp1 = fp2; in ironlake_compute_dpll()
8596 memset(&crtc_state->dpll_hw_state, 0, in ironlake_crtc_compute_clock()
8597 sizeof(crtc_state->dpll_hw_state)); in ironlake_crtc_compute_clock()
8947 &pipe_config->dpll_hw_state)); in ironlake_get_pipe_config()
8949 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
9468 &pipe_config->dpll_hw_state)); in haswell_get_ddi_port_state()
10278 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
10297 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
10304 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
10306 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
10963 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); in intel_dump_pipe_config()
11067 struct intel_dpll_hw_state dpll_hw_state; in clear_intel_crtc_state() local
11079 dpll_hw_state = crtc_state->dpll_hw_state; in clear_intel_crtc_state()
11093 crtc_state->dpll_hw_state = dpll_hw_state; in clear_intel_crtc_state()
11547 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
11548 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); in intel_pipe_config_compare()
11549 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); in intel_pipe_config_compare()
11550 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); in intel_pipe_config_compare()
11551 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); in intel_pipe_config_compare()
11552 PIPE_CONF_CHECK_X(dpll_hw_state.spll); in intel_pipe_config_compare()
11553 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); in intel_pipe_config_compare()
11554 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()
11555 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); in intel_pipe_config_compare()
11556 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
11557 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); in intel_pipe_config_compare()
11558 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); in intel_pipe_config_compare()
11559 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); in intel_pipe_config_compare()
11560 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); in intel_pipe_config_compare()
11561 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); in intel_pipe_config_compare()
11562 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); in intel_pipe_config_compare()
11563 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); in intel_pipe_config_compare()
11564 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); in intel_pipe_config_compare()
11565 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); in intel_pipe_config_compare()
11566 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); in intel_pipe_config_compare()
11567 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); in intel_pipe_config_compare()
11568 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); in intel_pipe_config_compare()
11569 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); in intel_pipe_config_compare()
11570 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); in intel_pipe_config_compare()
11571 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); in intel_pipe_config_compare()
11572 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); in intel_pipe_config_compare()
11573 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); in intel_pipe_config_compare()
11574 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); in intel_pipe_config_compare()
11575 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); in intel_pipe_config_compare()
11576 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); in intel_pipe_config_compare()
11577 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); in intel_pipe_config_compare()
11905 struct intel_dpll_hw_state dpll_hw_state; in verify_single_dpll_state() local
11909 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); in verify_single_dpll_state()
11913 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); in verify_single_dpll_state()
11949 &dpll_hw_state, in verify_single_dpll_state()
11950 sizeof(dpll_hw_state)), in verify_single_dpll_state()