7008 	u32 dpio_val;  in chv_prepare_pll()  local
7026 	dpio_val = 0;  in chv_prepare_pll()
7050 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_prepare_pll()
7051 	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);  in chv_prepare_pll()
7052 	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);  in chv_prepare_pll()
7054 		dpio_val |= DPIO_CHV_FRAC_DIV_EN;  in chv_prepare_pll()
7055 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);  in chv_prepare_pll()
7058 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));  in chv_prepare_pll()
7059 	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |  in chv_prepare_pll()
7061 	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);  in chv_prepare_pll()
7063 		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;  in chv_prepare_pll()
7064 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);  in chv_prepare_pll()
7091 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));  in chv_prepare_pll()
7092 	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;  in chv_prepare_pll()
7093 	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);  in chv_prepare_pll()
7094 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);  in chv_prepare_pll()