6536 	    crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)  in hsw_compute_ips_config()
9134 	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");  in hsw_restore_lcpll()
12219 	intel_state->cdclk.logical = dev_priv->cdclk.logical;  in intel_modeset_checks()
12220 	intel_state->cdclk.actual = dev_priv->cdclk.actual;  in intel_modeset_checks()
12249 		if (intel_cdclk_changed(&dev_priv->cdclk.logical,  in intel_modeset_checks()
12250 					&intel_state->cdclk.logical)) {  in intel_modeset_checks()
12257 		if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,  in intel_modeset_checks()
12258 					      &intel_state->cdclk.actual)) {  in intel_modeset_checks()
12265 			      intel_state->cdclk.logical.cdclk,  in intel_modeset_checks()
12266 			      intel_state->cdclk.actual.cdclk);  in intel_modeset_checks()
12268 			      intel_state->cdclk.logical.voltage_level,  in intel_modeset_checks()
12269 			      intel_state->cdclk.actual.voltage_level);  in intel_modeset_checks()
12271 		to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;  in intel_modeset_checks()
12367 		intel_state->cdclk.logical = dev_priv->cdclk.logical;  in intel_atomic_check()
12654 		intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);  in intel_atomic_commit_tail()
12874 		dev_priv->cdclk.logical = intel_state->cdclk.logical;  in intel_atomic_commit()
12875 		dev_priv->cdclk.actual = intel_state->cdclk.actual;  in intel_atomic_commit()
13171 	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;  in skl_max_scale()
15029 	intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");  in intel_modeset_init_hw()
15030 	dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;  in intel_modeset_init_hw()