3227 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in i9xx_plane_ctl()
3290 	if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {  in i9xx_check_plane_surface()
3353 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in i9xx_update_plane()
5019 		if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))  in ironlake_pfit_enable()
5744 	if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {  in haswell_crtc_enable()
6386 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in ironlake_check_fdi_lanes()
7325 	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&  in intel_set_pipe_timings()
7759 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in i9xx_get_initial_plane_config()
8418 	if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)  in haswell_set_pipeconf()
8989 	if (IS_HASWELL(dev_priv))  in assert_can_disable_lcpll()
9009 	if (IS_HASWELL(dev_priv))  in hsw_read_dcomp()
9017 	if (IS_HASWELL(dev_priv)) {  in hsw_write_dcomp()
9553 		if (IS_HASWELL(dev_priv))  in haswell_get_pipe_config()
11499 	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||  in intel_pipe_config_compare()
12276 	if (IS_HASWELL(dev_priv))  in intel_modeset_checks()
13602 	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))  in i9xx_plane_has_fbc()
14700 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {  in intel_mode_valid()
14827 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in intel_init_display_hooks()
15774 	if (IS_HASWELL(dev_priv)) {  in intel_early_display_was()
16079 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_display_capture_error_state()
16100 		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))  in intel_display_capture_error_state()
16154 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_display_print_error_state()
16171 		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))  in intel_display_print_error_state()