223 	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))  in intel_update_czclk()
623 	    !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))  in intel_PLL_is_valid()
627 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&  in intel_PLL_is_valid()
858 	if (IS_CHERRYVIEW(to_i915(dev))) {  in vlv_PLL_is_optimal()
1234 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in assert_panel_unlocked()
2037 		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_linear_alignment()
3342 	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {  in i9xx_update_plane()
6004 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {  in valleyview_crtc_enable()
6019 	if (IS_CHERRYVIEW(dev_priv)) {  in valleyview_crtc_enable()
6145 		if (IS_CHERRYVIEW(dev_priv))  in i9xx_crtc_disable()
6826 		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||  in intel_cpu_transcoder_set_m_n()
7128 	if (IS_CHERRYVIEW(dev_priv)) {  in vlv_force_pll_on()
7153 	if (IS_CHERRYVIEW(dev_priv))  in vlv_force_pll_off()
7434 	    IS_CHERRYVIEW(dev_priv)) {  in i9xx_set_pipeconf()
7465 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in i9xx_set_pipeconf()
7848 	    IS_CHERRYVIEW(dev_priv)) {  in i9xx_get_pipe_config()
7864 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in i9xx_get_pipe_config()
7878 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)  in i9xx_get_pipe_config()
7899 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {  in i9xx_get_pipe_config()
7917 	if (IS_CHERRYVIEW(dev_priv))  in i9xx_get_pipe_config()
9930 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&  in i9xx_check_cursor()
10799 	    IS_CHERRYVIEW(dev_priv)))  in compute_baseline_pipe_bpp()
11083 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in clear_intel_crtc_state()
11097 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in clear_intel_crtc_state()
11500 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_pipe_config_compare()
13784 	} else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {  in intel_primary_plane_create()
14076 	if (IS_CHERRYVIEW(dev_priv))  in intel_crt_present()
14104 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_pps_unlock_regs_wa()
14121 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_pps_init()
14225 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_setup_outputs()
14257 		if (IS_CHERRYVIEW(dev_priv)) {  in intel_setup_outputs()
14517 		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&  in intel_framebuffer_init()
14534 		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {  in intel_framebuffer_init()
14776 	} else if (IS_CHERRYVIEW(dev_priv)) {  in intel_init_display_hooks()
15835 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_modeset_setup_hw_state()