1307 			       enum intel_dpll_id pll_id)  in skl_calc_wrpll_link()  argument
1313 	cfgcr1_reg = DPLL_CFGCR1(pll_id);  in skl_calc_wrpll_link()
1314 	cfgcr2_reg = DPLL_CFGCR2(pll_id);  in skl_calc_wrpll_link()
1367 			       enum intel_dpll_id pll_id)  in cnl_calc_wrpll_link()  argument
1373 		cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));  in cnl_calc_wrpll_link()
1374 		cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));  in cnl_calc_wrpll_link()
1376 		cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));  in cnl_calc_wrpll_link()
1377 		cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));  in cnl_calc_wrpll_link()
1460 	uint32_t pll_id;  in icl_ddi_clock_get()  local
1462 	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);  in icl_ddi_clock_get()
1465 			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);  in icl_ddi_clock_get()
1468 								pll_id);  in icl_ddi_clock_get()
1484 	enum intel_dpll_id pll_id;  in cnl_ddi_clock_get()  local
1486 	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);  in cnl_ddi_clock_get()
1488 	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));  in cnl_ddi_clock_get()
1491 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);  in cnl_ddi_clock_get()
1538 	enum intel_dpll_id pll_id;  in skl_ddi_clock_get()  local
1540 	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);  in skl_ddi_clock_get()
1544 	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {  in skl_ddi_clock_get()
1545 		link_clock = skl_calc_wrpll_link(dev_priv, pll_id);  in skl_ddi_clock_get()
1547 		link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);  in skl_ddi_clock_get()
1548 		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);  in skl_ddi_clock_get()