240 	u32 *payload = dev_priv->csr.dmc_payload;  in intel_csr_load_program()
248 	if (!dev_priv->csr.dmc_payload) {  in intel_csr_load_program()
253 	fw_size = dev_priv->csr.dmc_fw_size;  in intel_csr_load_program()
263 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {  in intel_csr_load_program()
264 		I915_WRITE(dev_priv->csr.mmioaddr[i],  in intel_csr_load_program()
265 			   dev_priv->csr.mmiodata[i]);  in intel_csr_load_program()
268 	dev_priv->csr.dc_state = 0;  in intel_csr_load_program()
279 	struct intel_csr *csr = &dev_priv->csr;  in parse_csr_fw()  local
299 	csr->version = css_header->version;  in parse_csr_fw()
301 	if (csr->fw_path == i915_modparams.dmc_firmware_path) {  in parse_csr_fw()
303 		required_version = csr->version;  in parse_csr_fw()
319 	if (csr->version != required_version) {  in parse_csr_fw()
322 			 CSR_VERSION_MAJOR(csr->version),  in parse_csr_fw()
323 			 CSR_VERSION_MINOR(csr->version),  in parse_csr_fw()
375 	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {  in parse_csr_fw()
380 	csr->mmio_count = dmc_header->mmio_count;  in parse_csr_fw()
388 		csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);  in parse_csr_fw()
389 		csr->mmiodata[i] = dmc_header->mmiodata[i];  in parse_csr_fw()
398 	csr->dmc_fw_size = dmc_header->fw_size;  in parse_csr_fw()
412 	struct intel_csr *csr;  in csr_load_work_fn()  local
415 	dev_priv = container_of(work, typeof(*dev_priv), csr.work);  in csr_load_work_fn()
416 	csr = &dev_priv->csr;  in csr_load_work_fn()
418 	request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);  in csr_load_work_fn()
420 		dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);  in csr_load_work_fn()
422 	if (dev_priv->csr.dmc_payload) {  in csr_load_work_fn()
428 			 dev_priv->csr.fw_path,  in csr_load_work_fn()
429 			 CSR_VERSION_MAJOR(csr->version),  in csr_load_work_fn()
430 			 CSR_VERSION_MINOR(csr->version));  in csr_load_work_fn()
435 			   csr->fw_path);  in csr_load_work_fn()
452 	struct intel_csr *csr = &dev_priv->csr;  in intel_csr_ucode_init()  local
454 	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);  in intel_csr_ucode_init()
460 		csr->fw_path = i915_modparams.dmc_firmware_path;  in intel_csr_ucode_init()
462 		csr->fw_path = I915_CSR_CNL;  in intel_csr_ucode_init()
464 		csr->fw_path = I915_CSR_GLK;  in intel_csr_ucode_init()
466 		csr->fw_path = I915_CSR_KBL;  in intel_csr_ucode_init()
468 		csr->fw_path = I915_CSR_SKL;  in intel_csr_ucode_init()
470 		csr->fw_path = I915_CSR_BXT;  in intel_csr_ucode_init()
476 	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);  in intel_csr_ucode_init()
484 	schedule_work(&dev_priv->csr.work);  in intel_csr_ucode_init()
500 	flush_work(&dev_priv->csr.work);  in intel_csr_ucode_suspend()
503 	if (!dev_priv->csr.dmc_payload)  in intel_csr_ucode_suspend()
523 	if (!dev_priv->csr.dmc_payload)  in intel_csr_ucode_resume()
541 	kfree(dev_priv->csr.dmc_payload);  in intel_csr_ucode_fini()