220 	unsigned int vco;  in intel_hpll_vco()  local
239 	vco = vco_table[tmp & 0x7];  in intel_hpll_vco()
240 	if (vco == 0)  in intel_hpll_vco()
243 		DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);  in intel_hpll_vco()
245 	return vco;  in intel_hpll_vco()
260 	cdclk_state->vco = intel_hpll_vco(dev_priv);  in g33_get_cdclk()
269 	switch (cdclk_state->vco) {  in g33_get_cdclk()
286 	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,  in g33_get_cdclk()
292 		  cdclk_state->vco, tmp);  in g33_get_cdclk()
340 	cdclk_state->vco = intel_hpll_vco(dev_priv);  in i965gm_get_cdclk()
349 	switch (cdclk_state->vco) {  in i965gm_get_cdclk()
363 	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,  in i965gm_get_cdclk()
369 		  cdclk_state->vco, tmp);  in i965gm_get_cdclk()
380 	cdclk_state->vco = intel_hpll_vco(dev_priv);  in gm45_get_cdclk()
386 	switch (cdclk_state->vco) {  in gm45_get_cdclk()
397 			  cdclk_state->vco, tmp);  in gm45_get_cdclk()
465 	cdclk_state->vco = vlv_get_hpll_vco(dev_priv);  in vlv_get_cdclk()
468 					       cdclk_state->vco);  in vlv_get_cdclk()
774 static int skl_calc_cdclk(int min_cdclk, int vco)  in skl_calc_cdclk()  argument
776 	if (vco == 8640000) {  in skl_calc_cdclk()
821 	cdclk_state->vco = 0;  in skl_dpll0_update()
843 		cdclk_state->vco = 8100000;  in skl_dpll0_update()
847 		cdclk_state->vco = 8640000;  in skl_dpll0_update()
864 	if (cdclk_state->vco == 0)  in skl_get_cdclk()
869 	if (cdclk_state->vco == 8640000) {  in skl_get_cdclk()
923 					int vco)  in skl_set_preferred_cdclk_vco()  argument
925 	bool changed = dev_priv->skl_preferred_vco_freq != vco;  in skl_set_preferred_cdclk_vco()
927 	dev_priv->skl_preferred_vco_freq = vco;  in skl_set_preferred_cdclk_vco()
933 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)  in skl_dpll0_enable()  argument
937 	WARN_ON(vco != 8100000 && vco != 8640000);  in skl_dpll0_enable()
953 	if (vco == 8640000)  in skl_dpll0_enable()
970 	dev_priv->cdclk.hw.vco = vco;  in skl_dpll0_enable()
973 	skl_set_preferred_cdclk_vco(dev_priv, vco);  in skl_dpll0_enable()
984 	dev_priv->cdclk.hw.vco = 0;  in skl_dpll0_disable()
991 	int vco = cdclk_state->vco;  in skl_set_cdclk()  local
1003 	WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);  in skl_set_cdclk()
1021 		WARN_ON(vco != 0);  in skl_set_cdclk()
1040 	if (dev_priv->cdclk.hw.vco != 0 &&  in skl_set_cdclk()
1041 	    dev_priv->cdclk.hw.vco != vco)  in skl_set_cdclk()
1046 	if (dev_priv->cdclk.hw.vco != vco) {  in skl_set_cdclk()
1058 	if (dev_priv->cdclk.hw.vco != vco)  in skl_set_cdclk()
1059 		skl_dpll0_enable(dev_priv, vco);  in skl_set_cdclk()
1098 	if (dev_priv->cdclk.hw.vco == 0 ||  in skl_sanitize_cdclk()
1121 	dev_priv->cdclk.hw.vco = -1;  in skl_sanitize_cdclk()
1140 	    dev_priv->cdclk.hw.vco != 0) {  in skl_init_cdclk()
1147 						    dev_priv->cdclk.hw.vco);  in skl_init_cdclk()
1153 	cdclk_state.vco = dev_priv->skl_preferred_vco_freq;  in skl_init_cdclk()
1154 	if (cdclk_state.vco == 0)  in skl_init_cdclk()
1155 		cdclk_state.vco = 8100000;  in skl_init_cdclk()
1156 	cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);  in skl_init_cdclk()
1174 	cdclk_state.vco = 0;  in skl_uninit_cdclk()
1261 	cdclk_state->vco = 0;  in bxt_de_pll_update()
1271 	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;  in bxt_de_pll_update()
1284 	if (cdclk_state->vco == 0)  in bxt_get_cdclk()
1308 	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);  in bxt_get_cdclk()
1329 	dev_priv->cdclk.hw.vco = 0;  in bxt_de_pll_disable()
1332 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)  in bxt_de_pll_enable()  argument
1334 	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);  in bxt_de_pll_enable()
1352 	dev_priv->cdclk.hw.vco = vco;  in bxt_de_pll_enable()
1359 	int vco = cdclk_state->vco;  in bxt_set_cdclk()  local
1364 	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {  in bxt_set_cdclk()
1367 		WARN_ON(vco != 0);  in bxt_set_cdclk()
1401 	if (dev_priv->cdclk.hw.vco != 0 &&  in bxt_set_cdclk()
1402 	    dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1405 	if (dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1406 		bxt_de_pll_enable(dev_priv, vco);  in bxt_set_cdclk()
1450 	if (dev_priv->cdclk.hw.vco == 0 ||  in bxt_sanitize_cdclk()
1488 	dev_priv->cdclk.hw.vco = -1;  in bxt_sanitize_cdclk()
1507 	    dev_priv->cdclk.hw.vco != 0)  in bxt_init_cdclk()
1519 		cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);  in bxt_init_cdclk()
1522 		cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);  in bxt_init_cdclk()
1541 	cdclk_state.vco = 0;  in bxt_uninit_cdclk()
1580 	cdclk_state->vco = 0;  in cnl_cdclk_pll_update()
1589 	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;  in cnl_cdclk_pll_update()
1602 	if (cdclk_state->vco == 0)  in cnl_get_cdclk()
1619 	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);  in cnl_get_cdclk()
1642 	dev_priv->cdclk.hw.vco = 0;  in cnl_cdclk_pll_disable()
1645 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)  in cnl_cdclk_pll_enable()  argument
1647 	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);  in cnl_cdclk_pll_enable()
1660 	dev_priv->cdclk.hw.vco = vco;  in cnl_cdclk_pll_enable()
1667 	int vco = cdclk_state->vco;  in cnl_set_cdclk()  local
1684 	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {  in cnl_set_cdclk()
1687 		WARN_ON(vco != 0);  in cnl_set_cdclk()
1697 	if (dev_priv->cdclk.hw.vco != 0 &&  in cnl_set_cdclk()
1698 	    dev_priv->cdclk.hw.vco != vco)  in cnl_set_cdclk()
1701 	if (dev_priv->cdclk.hw.vco != vco)  in cnl_set_cdclk()
1702 		cnl_cdclk_pll_enable(dev_priv, vco);  in cnl_set_cdclk()
1757 	if (dev_priv->cdclk.hw.vco == 0 ||  in cnl_sanitize_cdclk()
1789 	dev_priv->cdclk.hw.vco = -1;  in cnl_sanitize_cdclk()
1851 	unsigned int vco = cdclk_state->vco;  in icl_set_cdclk()  local
1866 	if (dev_priv->cdclk.hw.vco != 0 &&  in icl_set_cdclk()
1867 	    dev_priv->cdclk.hw.vco != vco)  in icl_set_cdclk()
1870 	if (dev_priv->cdclk.hw.vco != vco)  in icl_set_cdclk()
1871 		cnl_cdclk_pll_enable(dev_priv, vco);  in icl_set_cdclk()
1939 		cdclk_state->vco = 0;  in icl_get_cdclk()
1944 	cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;  in icl_get_cdclk()
1949 	cdclk_state->cdclk = cdclk_state->vco / 2;  in icl_get_cdclk()
1998 	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,  in icl_init_cdclk()
2018 	cdclk_state.vco = 0;  in icl_uninit_cdclk()
2040 	    dev_priv->cdclk.hw.vco != 0)  in cnl_init_cdclk()
2046 	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);  in cnl_init_cdclk()
2064 	cdclk_state.vco = 0;  in cnl_uninit_cdclk()
2082 		a->vco != b->vco ||  in intel_cdclk_needs_modeset()
2105 			 context, cdclk_state->cdclk, cdclk_state->vco,  in intel_dump_cdclk_state()
2360 	int vco, i;  in skl_dpll0_vco()  local
2362 	vco = intel_state->cdclk.logical.vco;  in skl_dpll0_vco()
2363 	if (!vco)  in skl_dpll0_vco()
2364 		vco = dev_priv->skl_preferred_vco_freq;  in skl_dpll0_vco()
2380 			vco = 8640000;  in skl_dpll0_vco()
2383 			vco = 8100000;  in skl_dpll0_vco()
2388 	return vco;  in skl_dpll0_vco()
2394 	int min_cdclk, cdclk, vco;  in skl_modeset_calc_cdclk()  local
2400 	vco = skl_dpll0_vco(intel_state);  in skl_modeset_calc_cdclk()
2406 	cdclk = skl_calc_cdclk(min_cdclk, vco);  in skl_modeset_calc_cdclk()
2408 	intel_state->cdclk.logical.vco = vco;  in skl_modeset_calc_cdclk()
2414 		cdclk = skl_calc_cdclk(0, vco);  in skl_modeset_calc_cdclk()
2416 		intel_state->cdclk.actual.vco = vco;  in skl_modeset_calc_cdclk()
2432 	int min_cdclk, cdclk, vco;  in bxt_modeset_calc_cdclk()  local
2440 		vco = glk_de_pll_vco(dev_priv, cdclk);  in bxt_modeset_calc_cdclk()
2443 		vco = bxt_de_pll_vco(dev_priv, cdclk);  in bxt_modeset_calc_cdclk()
2446 	intel_state->cdclk.logical.vco = vco;  in bxt_modeset_calc_cdclk()
2454 			vco = glk_de_pll_vco(dev_priv, cdclk);  in bxt_modeset_calc_cdclk()
2457 			vco = bxt_de_pll_vco(dev_priv, cdclk);  in bxt_modeset_calc_cdclk()
2460 		intel_state->cdclk.actual.vco = vco;  in bxt_modeset_calc_cdclk()
2476 	int min_cdclk, cdclk, vco;  in cnl_modeset_calc_cdclk()  local
2483 	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);  in cnl_modeset_calc_cdclk()
2485 	intel_state->cdclk.logical.vco = vco;  in cnl_modeset_calc_cdclk()
2493 		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);  in cnl_modeset_calc_cdclk()
2495 		intel_state->cdclk.actual.vco = vco;  in cnl_modeset_calc_cdclk()
2512 	int min_cdclk, cdclk, vco;  in icl_modeset_calc_cdclk()  local
2519 	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);  in icl_modeset_calc_cdclk()
2521 	intel_state->cdclk.logical.vco = vco;  in icl_modeset_calc_cdclk()
2529 		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);  in icl_modeset_calc_cdclk()
2531 		intel_state->cdclk.actual.vco = vco;  in icl_modeset_calc_cdclk()
2584 		int max_cdclk, vco;  in intel_update_max_cdclk()  local
2586 		vco = dev_priv->skl_preferred_vco_freq;  in intel_update_max_cdclk()
2587 		WARN_ON(vco != 8100000 && vco != 8640000);  in intel_update_max_cdclk()
2603 		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);  in intel_update_max_cdclk()