136 	u16 gcfgc = 0;  in i915gm_get_cdclk()  local
138 	pci_read_config_word(pdev, GCFGC, &gcfgc);  in i915gm_get_cdclk()
140 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {  in i915gm_get_cdclk()
145 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {  in i915gm_get_cdclk()
160 	u16 gcfgc = 0;  in i945gm_get_cdclk()  local
162 	pci_read_config_word(pdev, GCFGC, &gcfgc);  in i945gm_get_cdclk()
164 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {  in i945gm_get_cdclk()
169 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {  in i945gm_get_cdclk()
300 	u16 gcfgc = 0;  in pnv_get_cdclk()  local
302 	pci_read_config_word(pdev, GCFGC, &gcfgc);  in pnv_get_cdclk()
304 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {  in pnv_get_cdclk()
318 		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);  in pnv_get_cdclk()