Lines Matching refs:dev_priv
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
93 struct pci_dev *pdev = dev_priv->drm.pdev; in i85x_get_cdclk()
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
135 struct pci_dev *pdev = dev_priv->drm.pdev; in i915gm_get_cdclk()
156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, in i945gm_get_cdclk() argument
159 struct pci_dev *pdev = dev_priv->drm.pdev; in i945gm_get_cdclk()
180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) in intel_hpll_vco() argument
224 if (IS_GM45(dev_priv)) in intel_hpll_vco()
226 else if (IS_G45(dev_priv)) in intel_hpll_vco()
228 else if (IS_I965GM(dev_priv)) in intel_hpll_vco()
230 else if (IS_PINEVIEW(dev_priv)) in intel_hpll_vco()
232 else if (IS_G33(dev_priv)) in intel_hpll_vco()
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
248 static void g33_get_cdclk(struct drm_i915_private *dev_priv, in g33_get_cdclk() argument
251 struct pci_dev *pdev = dev_priv->drm.pdev; in g33_get_cdclk()
260 cdclk_state->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, in pnv_get_cdclk() argument
299 struct pci_dev *pdev = dev_priv->drm.pdev; in pnv_get_cdclk()
329 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, in i965gm_get_cdclk() argument
332 struct pci_dev *pdev = dev_priv->drm.pdev; in i965gm_get_cdclk()
340 cdclk_state->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
373 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, in gm45_get_cdclk() argument
376 struct pci_dev *pdev = dev_priv->drm.pdev; in gm45_get_cdclk()
380 cdclk_state->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
403 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, in hsw_get_cdclk() argument
415 else if (IS_HSW_ULT(dev_priv)) in hsw_get_cdclk()
421 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in vlv_calc_cdclk() argument
423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
431 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
441 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
443 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
456 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
460 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, in vlv_get_cdclk() argument
465 cdclk_state->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
466 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
470 mutex_lock(&dev_priv->pcu_lock); in vlv_get_cdclk()
471 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in vlv_get_cdclk()
472 mutex_unlock(&dev_priv->pcu_lock); in vlv_get_cdclk()
474 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
482 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
486 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
491 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
493 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
518 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, in vlv_set_cdclk() argument
542 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); in vlv_set_cdclk()
544 mutex_lock(&dev_priv->pcu_lock); in vlv_set_cdclk()
545 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in vlv_set_cdclk()
548 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); in vlv_set_cdclk()
549 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in vlv_set_cdclk()
554 mutex_unlock(&dev_priv->pcu_lock); in vlv_set_cdclk()
556 mutex_lock(&dev_priv->sb_lock); in vlv_set_cdclk()
561 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
565 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
568 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in vlv_set_cdclk()
570 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
577 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in vlv_set_cdclk()
588 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in vlv_set_cdclk()
590 mutex_unlock(&dev_priv->sb_lock); in vlv_set_cdclk()
592 intel_update_cdclk(dev_priv); in vlv_set_cdclk()
594 vlv_program_pfi_credits(dev_priv); in vlv_set_cdclk()
596 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); in vlv_set_cdclk()
599 static void chv_set_cdclk(struct drm_i915_private *dev_priv, in chv_set_cdclk() argument
622 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); in chv_set_cdclk()
624 mutex_lock(&dev_priv->pcu_lock); in chv_set_cdclk()
625 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in chv_set_cdclk()
628 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); in chv_set_cdclk()
629 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in chv_set_cdclk()
634 mutex_unlock(&dev_priv->pcu_lock); in chv_set_cdclk()
636 intel_update_cdclk(dev_priv); in chv_set_cdclk()
638 vlv_program_pfi_credits(dev_priv); in chv_set_cdclk()
640 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); in chv_set_cdclk()
670 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, in bdw_get_cdclk() argument
697 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, in bdw_set_cdclk() argument
712 mutex_lock(&dev_priv->pcu_lock); in bdw_set_cdclk()
713 ret = sandybridge_pcode_write(dev_priv, in bdw_set_cdclk()
715 mutex_unlock(&dev_priv->pcu_lock); in bdw_set_cdclk()
764 mutex_lock(&dev_priv->pcu_lock); in bdw_set_cdclk()
765 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
767 mutex_unlock(&dev_priv->pcu_lock); in bdw_set_cdclk()
771 intel_update_cdclk(dev_priv); in bdw_set_cdclk()
815 static void skl_dpll0_update(struct drm_i915_private *dev_priv, in skl_dpll0_update() argument
855 static void skl_get_cdclk(struct drm_i915_private *dev_priv, in skl_get_cdclk() argument
860 skl_dpll0_update(dev_priv, cdclk_state); in skl_get_cdclk()
922 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, in skl_set_preferred_cdclk_vco() argument
925 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
927 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
930 intel_update_max_cdclk(dev_priv); in skl_set_preferred_cdclk_vco()
933 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
965 if (intel_wait_for_register(dev_priv, in skl_dpll0_enable()
970 dev_priv->cdclk.hw.vco = vco; in skl_dpll0_enable()
973 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
976 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) in skl_dpll0_disable() argument
979 if (intel_wait_for_register(dev_priv, in skl_dpll0_disable()
984 dev_priv->cdclk.hw.vco = 0; in skl_dpll0_disable()
987 static void skl_set_cdclk(struct drm_i915_private *dev_priv, in skl_set_cdclk() argument
1003 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1005 mutex_lock(&dev_priv->pcu_lock); in skl_set_cdclk()
1006 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1010 mutex_unlock(&dev_priv->pcu_lock); in skl_set_cdclk()
1020 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in skl_set_cdclk()
1040 if (dev_priv->cdclk.hw.vco != 0 && in skl_set_cdclk()
1041 dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1042 skl_dpll0_disable(dev_priv); in skl_set_cdclk()
1046 if (dev_priv->cdclk.hw.vco != vco) { in skl_set_cdclk()
1058 if (dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1059 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1074 mutex_lock(&dev_priv->pcu_lock); in skl_set_cdclk()
1075 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1077 mutex_unlock(&dev_priv->pcu_lock); in skl_set_cdclk()
1079 intel_update_cdclk(dev_priv); in skl_set_cdclk()
1082 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) in skl_sanitize_cdclk() argument
1094 intel_update_cdclk(dev_priv); in skl_sanitize_cdclk()
1095 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1098 if (dev_priv->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1099 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1110 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1119 dev_priv->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1121 dev_priv->cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1133 void skl_init_cdclk(struct drm_i915_private *dev_priv) in skl_init_cdclk() argument
1137 skl_sanitize_cdclk(dev_priv); in skl_init_cdclk()
1139 if (dev_priv->cdclk.hw.cdclk != 0 && in skl_init_cdclk()
1140 dev_priv->cdclk.hw.vco != 0) { in skl_init_cdclk()
1145 if (dev_priv->skl_preferred_vco_freq == 0) in skl_init_cdclk()
1146 skl_set_preferred_cdclk_vco(dev_priv, in skl_init_cdclk()
1147 dev_priv->cdclk.hw.vco); in skl_init_cdclk()
1151 cdclk_state = dev_priv->cdclk.hw; in skl_init_cdclk()
1153 cdclk_state.vco = dev_priv->skl_preferred_vco_freq; in skl_init_cdclk()
1159 skl_set_cdclk(dev_priv, &cdclk_state); in skl_init_cdclk()
1169 void skl_uninit_cdclk(struct drm_i915_private *dev_priv) in skl_uninit_cdclk() argument
1171 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in skl_uninit_cdclk()
1177 skl_set_cdclk(dev_priv, &cdclk_state); in skl_uninit_cdclk()
1209 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_de_pll_vco() argument
1213 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_de_pll_vco()
1231 return dev_priv->cdclk.hw.ref * ratio; in bxt_de_pll_vco()
1234 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in glk_de_pll_vco() argument
1238 if (cdclk == dev_priv->cdclk.hw.bypass) in glk_de_pll_vco()
1252 return dev_priv->cdclk.hw.ref * ratio; in glk_de_pll_vco()
1255 static void bxt_de_pll_update(struct drm_i915_private *dev_priv, in bxt_de_pll_update() argument
1274 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, in bxt_get_cdclk() argument
1280 bxt_de_pll_update(dev_priv, cdclk_state); in bxt_get_cdclk()
1294 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); in bxt_get_cdclk()
1319 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) in bxt_de_pll_disable() argument
1324 if (intel_wait_for_register(dev_priv, in bxt_de_pll_disable()
1329 dev_priv->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1332 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1334 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable()
1345 if (intel_wait_for_register(dev_priv, in bxt_de_pll_enable()
1352 dev_priv->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1355 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, in bxt_set_cdclk() argument
1366 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in bxt_set_cdclk()
1373 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); in bxt_set_cdclk()
1389 mutex_lock(&dev_priv->pcu_lock); in bxt_set_cdclk()
1390 ret = sandybridge_pcode_write_timeout(dev_priv, in bxt_set_cdclk()
1393 mutex_unlock(&dev_priv->pcu_lock); in bxt_set_cdclk()
1401 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1402 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1403 bxt_de_pll_disable(dev_priv); in bxt_set_cdclk()
1405 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1406 bxt_de_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1422 mutex_lock(&dev_priv->pcu_lock); in bxt_set_cdclk()
1429 ret = sandybridge_pcode_write_timeout(dev_priv, in bxt_set_cdclk()
1432 mutex_unlock(&dev_priv->pcu_lock); in bxt_set_cdclk()
1440 intel_update_cdclk(dev_priv); in bxt_set_cdclk()
1443 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) in bxt_sanitize_cdclk() argument
1447 intel_update_cdclk(dev_priv); in bxt_sanitize_cdclk()
1448 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1450 if (dev_priv->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1451 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in bxt_sanitize_cdclk()
1469 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1474 if (dev_priv->cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1485 dev_priv->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1488 dev_priv->cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1500 void bxt_init_cdclk(struct drm_i915_private *dev_priv) in bxt_init_cdclk() argument
1504 bxt_sanitize_cdclk(dev_priv); in bxt_init_cdclk()
1506 if (dev_priv->cdclk.hw.cdclk != 0 && in bxt_init_cdclk()
1507 dev_priv->cdclk.hw.vco != 0) in bxt_init_cdclk()
1510 cdclk_state = dev_priv->cdclk.hw; in bxt_init_cdclk()
1517 if (IS_GEMINILAKE(dev_priv)) { in bxt_init_cdclk()
1519 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); in bxt_init_cdclk()
1522 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); in bxt_init_cdclk()
1526 bxt_set_cdclk(dev_priv, &cdclk_state); in bxt_init_cdclk()
1536 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) in bxt_uninit_cdclk() argument
1538 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in bxt_uninit_cdclk()
1544 bxt_set_cdclk(dev_priv, &cdclk_state); in bxt_uninit_cdclk()
1570 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, in cnl_cdclk_pll_update() argument
1592 static void cnl_get_cdclk(struct drm_i915_private *dev_priv, in cnl_get_cdclk() argument
1598 cnl_cdclk_pll_update(dev_priv, cdclk_state); in cnl_get_cdclk()
1630 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) in cnl_cdclk_pll_disable() argument
1642 dev_priv->cdclk.hw.vco = 0; in cnl_cdclk_pll_disable()
1645 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in cnl_cdclk_pll_enable() argument
1647 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in cnl_cdclk_pll_enable()
1660 dev_priv->cdclk.hw.vco = vco; in cnl_cdclk_pll_enable()
1663 static void cnl_set_cdclk(struct drm_i915_private *dev_priv, in cnl_set_cdclk() argument
1671 mutex_lock(&dev_priv->pcu_lock); in cnl_set_cdclk()
1672 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, in cnl_set_cdclk()
1676 mutex_unlock(&dev_priv->pcu_lock); in cnl_set_cdclk()
1686 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in cnl_set_cdclk()
1697 if (dev_priv->cdclk.hw.vco != 0 && in cnl_set_cdclk()
1698 dev_priv->cdclk.hw.vco != vco) in cnl_set_cdclk()
1699 cnl_cdclk_pll_disable(dev_priv); in cnl_set_cdclk()
1701 if (dev_priv->cdclk.hw.vco != vco) in cnl_set_cdclk()
1702 cnl_cdclk_pll_enable(dev_priv, vco); in cnl_set_cdclk()
1713 mutex_lock(&dev_priv->pcu_lock); in cnl_set_cdclk()
1714 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in cnl_set_cdclk()
1716 mutex_unlock(&dev_priv->pcu_lock); in cnl_set_cdclk()
1718 intel_update_cdclk(dev_priv); in cnl_set_cdclk()
1724 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; in cnl_set_cdclk()
1727 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in cnl_cdclk_pll_vco() argument
1731 if (cdclk == dev_priv->cdclk.hw.bypass) in cnl_cdclk_pll_vco()
1740 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; in cnl_cdclk_pll_vco()
1743 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; in cnl_cdclk_pll_vco()
1747 return dev_priv->cdclk.hw.ref * ratio; in cnl_cdclk_pll_vco()
1750 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv) in cnl_sanitize_cdclk() argument
1754 intel_update_cdclk(dev_priv); in cnl_sanitize_cdclk()
1755 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in cnl_sanitize_cdclk()
1757 if (dev_priv->cdclk.hw.vco == 0 || in cnl_sanitize_cdclk()
1758 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in cnl_sanitize_cdclk()
1776 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in cnl_sanitize_cdclk()
1786 dev_priv->cdclk.hw.cdclk = 0; in cnl_sanitize_cdclk()
1789 dev_priv->cdclk.hw.vco = -1; in cnl_sanitize_cdclk()
1819 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in icl_calc_cdclk_pll_vco() argument
1823 if (cdclk == dev_priv->cdclk.hw.bypass) in icl_calc_cdclk_pll_vco()
1833 WARN_ON(dev_priv->cdclk.hw.ref != 19200 && in icl_calc_cdclk_pll_vco()
1834 dev_priv->cdclk.hw.ref != 38400); in icl_calc_cdclk_pll_vco()
1839 WARN_ON(dev_priv->cdclk.hw.ref != 24000); in icl_calc_cdclk_pll_vco()
1842 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2); in icl_calc_cdclk_pll_vco()
1844 return dev_priv->cdclk.hw.ref * ratio; in icl_calc_cdclk_pll_vco()
1847 static void icl_set_cdclk(struct drm_i915_private *dev_priv, in icl_set_cdclk() argument
1854 mutex_lock(&dev_priv->pcu_lock); in icl_set_cdclk()
1855 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, in icl_set_cdclk()
1859 mutex_unlock(&dev_priv->pcu_lock); in icl_set_cdclk()
1866 if (dev_priv->cdclk.hw.vco != 0 && in icl_set_cdclk()
1867 dev_priv->cdclk.hw.vco != vco) in icl_set_cdclk()
1868 cnl_cdclk_pll_disable(dev_priv); in icl_set_cdclk()
1870 if (dev_priv->cdclk.hw.vco != vco) in icl_set_cdclk()
1871 cnl_cdclk_pll_enable(dev_priv, vco); in icl_set_cdclk()
1876 mutex_lock(&dev_priv->pcu_lock); in icl_set_cdclk()
1877 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in icl_set_cdclk()
1879 mutex_unlock(&dev_priv->pcu_lock); in icl_set_cdclk()
1881 intel_update_cdclk(dev_priv); in icl_set_cdclk()
1887 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; in icl_set_cdclk()
1909 static void icl_get_cdclk(struct drm_i915_private *dev_priv, in icl_get_cdclk() argument
1969 void icl_init_cdclk(struct drm_i915_private *dev_priv) in icl_init_cdclk() argument
1975 intel_update_cdclk(dev_priv); in icl_init_cdclk()
1976 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in icl_init_cdclk()
1979 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in icl_init_cdclk()
1988 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk)) in icl_init_cdclk()
1996 sanitized_state.ref = dev_priv->cdclk.hw.ref; in icl_init_cdclk()
1998 sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv, in icl_init_cdclk()
2003 icl_set_cdclk(dev_priv, &sanitized_state); in icl_init_cdclk()
2013 void icl_uninit_cdclk(struct drm_i915_private *dev_priv) in icl_uninit_cdclk() argument
2015 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in icl_uninit_cdclk()
2021 icl_set_cdclk(dev_priv, &cdclk_state); in icl_uninit_cdclk()
2033 void cnl_init_cdclk(struct drm_i915_private *dev_priv) in cnl_init_cdclk() argument
2037 cnl_sanitize_cdclk(dev_priv); in cnl_init_cdclk()
2039 if (dev_priv->cdclk.hw.cdclk != 0 && in cnl_init_cdclk()
2040 dev_priv->cdclk.hw.vco != 0) in cnl_init_cdclk()
2043 cdclk_state = dev_priv->cdclk.hw; in cnl_init_cdclk()
2046 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); in cnl_init_cdclk()
2049 cnl_set_cdclk(dev_priv, &cdclk_state); in cnl_init_cdclk()
2059 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv) in cnl_uninit_cdclk() argument
2061 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in cnl_uninit_cdclk()
2067 cnl_set_cdclk(dev_priv, &cdclk_state); in cnl_uninit_cdclk()
2118 void intel_set_cdclk(struct drm_i915_private *dev_priv, in intel_set_cdclk() argument
2121 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) in intel_set_cdclk()
2124 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) in intel_set_cdclk()
2129 dev_priv->display.set_cdclk(dev_priv, cdclk_state); in intel_set_cdclk()
2131 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), in intel_set_cdclk()
2133 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2138 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, in intel_pixel_rate_to_cdclk() argument
2141 if (INTEL_GEN(dev_priv) >= 10) in intel_pixel_rate_to_cdclk()
2143 else if (IS_GEMINILAKE(dev_priv)) in intel_pixel_rate_to_cdclk()
2151 else if (IS_GEN9(dev_priv) || in intel_pixel_rate_to_cdclk()
2152 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2154 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2162 struct drm_i915_private *dev_priv = in intel_crtc_compute_min_cdclk() local
2169 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); in intel_crtc_compute_min_cdclk()
2172 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) in intel_crtc_compute_min_cdclk()
2184 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { in intel_crtc_compute_min_cdclk()
2187 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { in intel_crtc_compute_min_cdclk()
2208 if (INTEL_GEN(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2216 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2219 if (min_cdclk > dev_priv->max_cdclk_freq) { in intel_crtc_compute_min_cdclk()
2221 min_cdclk, dev_priv->max_cdclk_freq); in intel_crtc_compute_min_cdclk()
2231 struct drm_i915_private *dev_priv = to_i915(state->dev); in intel_compute_min_cdclk() local
2237 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk, in intel_compute_min_cdclk()
2249 for_each_pipe(dev_priv, pipe) in intel_compute_min_cdclk()
2266 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in cnl_compute_min_voltage_level() local
2273 memcpy(state->min_voltage_level, dev_priv->min_voltage_level, in cnl_compute_min_voltage_level()
2285 for_each_pipe(dev_priv, pipe) in cnl_compute_min_voltage_level()
2294 struct drm_i915_private *dev_priv = to_i915(state->dev); in vlv_modeset_calc_cdclk() local
2302 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2306 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2309 cdclk = vlv_calc_cdclk(dev_priv, 0); in vlv_modeset_calc_cdclk()
2313 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2357 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); in skl_dpll0_vco() local
2364 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2430 struct drm_i915_private *dev_priv = to_i915(state->dev); in bxt_modeset_calc_cdclk() local
2438 if (IS_GEMINILAKE(dev_priv)) { in bxt_modeset_calc_cdclk()
2440 vco = glk_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2443 vco = bxt_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2452 if (IS_GEMINILAKE(dev_priv)) { in bxt_modeset_calc_cdclk()
2454 vco = glk_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2457 vco = bxt_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2474 struct drm_i915_private *dev_priv = to_i915(state->dev); in cnl_modeset_calc_cdclk() local
2483 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); in cnl_modeset_calc_cdclk()
2493 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); in cnl_modeset_calc_cdclk()
2509 struct drm_i915_private *dev_priv = to_i915(state->dev); in icl_modeset_calc_cdclk() local
2519 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); in icl_modeset_calc_cdclk()
2529 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); in icl_modeset_calc_cdclk()
2542 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) in intel_compute_max_dotclk() argument
2544 int max_cdclk_freq = dev_priv->max_cdclk_freq; in intel_compute_max_dotclk()
2546 if (INTEL_GEN(dev_priv) >= 10) in intel_compute_max_dotclk()
2548 else if (IS_GEMINILAKE(dev_priv)) in intel_compute_max_dotclk()
2554 else if (IS_GEN9(dev_priv) || in intel_compute_max_dotclk()
2555 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
2557 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
2559 else if (INTEL_GEN(dev_priv) < 4) in intel_compute_max_dotclk()
2573 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) in intel_update_max_cdclk() argument
2575 if (IS_ICELAKE(dev_priv)) { in intel_update_max_cdclk()
2576 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2577 dev_priv->max_cdclk_freq = 648000; in intel_update_max_cdclk()
2579 dev_priv->max_cdclk_freq = 652800; in intel_update_max_cdclk()
2580 } else if (IS_CANNONLAKE(dev_priv)) { in intel_update_max_cdclk()
2581 dev_priv->max_cdclk_freq = 528000; in intel_update_max_cdclk()
2582 } else if (IS_GEN9_BC(dev_priv)) { in intel_update_max_cdclk()
2586 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2603 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2604 } else if (IS_GEMINILAKE(dev_priv)) { in intel_update_max_cdclk()
2605 dev_priv->max_cdclk_freq = 316800; in intel_update_max_cdclk()
2606 } else if (IS_BROXTON(dev_priv)) { in intel_update_max_cdclk()
2607 dev_priv->max_cdclk_freq = 624000; in intel_update_max_cdclk()
2608 } else if (IS_BROADWELL(dev_priv)) { in intel_update_max_cdclk()
2616 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2617 else if (IS_BDW_ULX(dev_priv)) in intel_update_max_cdclk()
2618 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2619 else if (IS_BDW_ULT(dev_priv)) in intel_update_max_cdclk()
2620 dev_priv->max_cdclk_freq = 540000; in intel_update_max_cdclk()
2622 dev_priv->max_cdclk_freq = 675000; in intel_update_max_cdclk()
2623 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
2624 dev_priv->max_cdclk_freq = 320000; in intel_update_max_cdclk()
2625 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
2626 dev_priv->max_cdclk_freq = 400000; in intel_update_max_cdclk()
2629 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2632 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
2635 dev_priv->max_cdclk_freq); in intel_update_max_cdclk()
2638 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
2647 void intel_update_cdclk(struct drm_i915_private *dev_priv) in intel_update_cdclk() argument
2649 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2657 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
2659 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
2662 static int cnp_rawclk(struct drm_i915_private *dev_priv) in cnp_rawclk() argument
2686 static int icp_rawclk(struct drm_i915_private *dev_priv) in icp_rawclk() argument
2710 static int pch_rawclk(struct drm_i915_private *dev_priv) in pch_rawclk() argument
2715 static int vlv_hrawclk(struct drm_i915_private *dev_priv) in vlv_hrawclk() argument
2718 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", in vlv_hrawclk()
2722 static int g4x_hrawclk(struct drm_i915_private *dev_priv) in g4x_hrawclk() argument
2755 void intel_update_rawclk(struct drm_i915_private *dev_priv) in intel_update_rawclk() argument
2757 if (HAS_PCH_ICP(dev_priv)) in intel_update_rawclk()
2758 dev_priv->rawclk_freq = icp_rawclk(dev_priv); in intel_update_rawclk()
2759 else if (HAS_PCH_CNP(dev_priv)) in intel_update_rawclk()
2760 dev_priv->rawclk_freq = cnp_rawclk(dev_priv); in intel_update_rawclk()
2761 else if (HAS_PCH_SPLIT(dev_priv)) in intel_update_rawclk()
2762 dev_priv->rawclk_freq = pch_rawclk(dev_priv); in intel_update_rawclk()
2763 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_rawclk()
2764 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); in intel_update_rawclk()
2765 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) in intel_update_rawclk()
2766 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); in intel_update_rawclk()
2771 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); in intel_update_rawclk()
2778 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) in intel_init_cdclk_hooks() argument
2780 if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
2781 dev_priv->display.set_cdclk = chv_set_cdclk; in intel_init_cdclk_hooks()
2782 dev_priv->display.modeset_calc_cdclk = in intel_init_cdclk_hooks()
2784 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
2785 dev_priv->display.set_cdclk = vlv_set_cdclk; in intel_init_cdclk_hooks()
2786 dev_priv->display.modeset_calc_cdclk = in intel_init_cdclk_hooks()
2788 } else if (IS_BROADWELL(dev_priv)) { in intel_init_cdclk_hooks()
2789 dev_priv->display.set_cdclk = bdw_set_cdclk; in intel_init_cdclk_hooks()
2790 dev_priv->display.modeset_calc_cdclk = in intel_init_cdclk_hooks()
2792 } else if (IS_GEN9_LP(dev_priv)) { in intel_init_cdclk_hooks()
2793 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2794 dev_priv->display.modeset_calc_cdclk = in intel_init_cdclk_hooks()
2796 } else if (IS_GEN9_BC(dev_priv)) { in intel_init_cdclk_hooks()
2797 dev_priv->display.set_cdclk = skl_set_cdclk; in intel_init_cdclk_hooks()
2798 dev_priv->display.modeset_calc_cdclk = in intel_init_cdclk_hooks()
2800 } else if (IS_CANNONLAKE(dev_priv)) { in intel_init_cdclk_hooks()
2801 dev_priv->display.set_cdclk = cnl_set_cdclk; in intel_init_cdclk_hooks()
2802 dev_priv->display.modeset_calc_cdclk = in intel_init_cdclk_hooks()
2804 } else if (IS_ICELAKE(dev_priv)) { in intel_init_cdclk_hooks()
2805 dev_priv->display.set_cdclk = icl_set_cdclk; in intel_init_cdclk_hooks()
2806 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2809 if (IS_ICELAKE(dev_priv)) in intel_init_cdclk_hooks()
2810 dev_priv->display.get_cdclk = icl_get_cdclk; in intel_init_cdclk_hooks()
2811 else if (IS_CANNONLAKE(dev_priv)) in intel_init_cdclk_hooks()
2812 dev_priv->display.get_cdclk = cnl_get_cdclk; in intel_init_cdclk_hooks()
2813 else if (IS_GEN9_BC(dev_priv)) in intel_init_cdclk_hooks()
2814 dev_priv->display.get_cdclk = skl_get_cdclk; in intel_init_cdclk_hooks()
2815 else if (IS_GEN9_LP(dev_priv)) in intel_init_cdclk_hooks()
2816 dev_priv->display.get_cdclk = bxt_get_cdclk; in intel_init_cdclk_hooks()
2817 else if (IS_BROADWELL(dev_priv)) in intel_init_cdclk_hooks()
2818 dev_priv->display.get_cdclk = bdw_get_cdclk; in intel_init_cdclk_hooks()
2819 else if (IS_HASWELL(dev_priv)) in intel_init_cdclk_hooks()
2820 dev_priv->display.get_cdclk = hsw_get_cdclk; in intel_init_cdclk_hooks()
2821 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_init_cdclk_hooks()
2822 dev_priv->display.get_cdclk = vlv_get_cdclk; in intel_init_cdclk_hooks()
2823 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) in intel_init_cdclk_hooks()
2824 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2825 else if (IS_GEN5(dev_priv)) in intel_init_cdclk_hooks()
2826 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; in intel_init_cdclk_hooks()
2827 else if (IS_GM45(dev_priv)) in intel_init_cdclk_hooks()
2828 dev_priv->display.get_cdclk = gm45_get_cdclk; in intel_init_cdclk_hooks()
2829 else if (IS_G45(dev_priv)) in intel_init_cdclk_hooks()
2830 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2831 else if (IS_I965GM(dev_priv)) in intel_init_cdclk_hooks()
2832 dev_priv->display.get_cdclk = i965gm_get_cdclk; in intel_init_cdclk_hooks()
2833 else if (IS_I965G(dev_priv)) in intel_init_cdclk_hooks()
2834 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2835 else if (IS_PINEVIEW(dev_priv)) in intel_init_cdclk_hooks()
2836 dev_priv->display.get_cdclk = pnv_get_cdclk; in intel_init_cdclk_hooks()
2837 else if (IS_G33(dev_priv)) in intel_init_cdclk_hooks()
2838 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2839 else if (IS_I945GM(dev_priv)) in intel_init_cdclk_hooks()
2840 dev_priv->display.get_cdclk = i945gm_get_cdclk; in intel_init_cdclk_hooks()
2841 else if (IS_I945G(dev_priv)) in intel_init_cdclk_hooks()
2842 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2843 else if (IS_I915GM(dev_priv)) in intel_init_cdclk_hooks()
2844 dev_priv->display.get_cdclk = i915gm_get_cdclk; in intel_init_cdclk_hooks()
2845 else if (IS_I915G(dev_priv)) in intel_init_cdclk_hooks()
2846 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; in intel_init_cdclk_hooks()
2847 else if (IS_I865G(dev_priv)) in intel_init_cdclk_hooks()
2848 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; in intel_init_cdclk_hooks()
2849 else if (IS_I85X(dev_priv)) in intel_init_cdclk_hooks()
2850 dev_priv->display.get_cdclk = i85x_get_cdclk; in intel_init_cdclk_hooks()
2851 else if (IS_I845G(dev_priv)) in intel_init_cdclk_hooks()
2852 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; in intel_init_cdclk_hooks()
2854 WARN(!IS_I830(dev_priv), in intel_init_cdclk_hooks()
2856 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()