Lines Matching refs:cdclk_state
55 struct intel_cdclk_state *cdclk_state) in fixed_133mhz_get_cdclk() argument
57 cdclk_state->cdclk = 133333; in fixed_133mhz_get_cdclk()
61 struct intel_cdclk_state *cdclk_state) in fixed_200mhz_get_cdclk() argument
63 cdclk_state->cdclk = 200000; in fixed_200mhz_get_cdclk()
67 struct intel_cdclk_state *cdclk_state) in fixed_266mhz_get_cdclk() argument
69 cdclk_state->cdclk = 266667; in fixed_266mhz_get_cdclk()
73 struct intel_cdclk_state *cdclk_state) in fixed_333mhz_get_cdclk() argument
75 cdclk_state->cdclk = 333333; in fixed_333mhz_get_cdclk()
79 struct intel_cdclk_state *cdclk_state) in fixed_400mhz_get_cdclk() argument
81 cdclk_state->cdclk = 400000; in fixed_400mhz_get_cdclk()
85 struct intel_cdclk_state *cdclk_state) in fixed_450mhz_get_cdclk() argument
87 cdclk_state->cdclk = 450000; in fixed_450mhz_get_cdclk()
91 struct intel_cdclk_state *cdclk_state) in i85x_get_cdclk() argument
102 cdclk_state->cdclk = 133333; in i85x_get_cdclk()
116 cdclk_state->cdclk = 200000; in i85x_get_cdclk()
119 cdclk_state->cdclk = 250000; in i85x_get_cdclk()
122 cdclk_state->cdclk = 133333; in i85x_get_cdclk()
127 cdclk_state->cdclk = 266667; in i85x_get_cdclk()
133 struct intel_cdclk_state *cdclk_state) in i915gm_get_cdclk() argument
141 cdclk_state->cdclk = 133333; in i915gm_get_cdclk()
147 cdclk_state->cdclk = 333333; in i915gm_get_cdclk()
151 cdclk_state->cdclk = 190000; in i915gm_get_cdclk()
157 struct intel_cdclk_state *cdclk_state) in i945gm_get_cdclk() argument
165 cdclk_state->cdclk = 133333; in i945gm_get_cdclk()
171 cdclk_state->cdclk = 320000; in i945gm_get_cdclk()
175 cdclk_state->cdclk = 200000; in i945gm_get_cdclk()
249 struct intel_cdclk_state *cdclk_state) in g33_get_cdclk() argument
260 cdclk_state->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
269 switch (cdclk_state->vco) { in g33_get_cdclk()
286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, in g33_get_cdclk()
292 cdclk_state->vco, tmp); in g33_get_cdclk()
293 cdclk_state->cdclk = 190476; in g33_get_cdclk()
297 struct intel_cdclk_state *cdclk_state) in pnv_get_cdclk() argument
306 cdclk_state->cdclk = 266667; in pnv_get_cdclk()
309 cdclk_state->cdclk = 333333; in pnv_get_cdclk()
312 cdclk_state->cdclk = 444444; in pnv_get_cdclk()
315 cdclk_state->cdclk = 200000; in pnv_get_cdclk()
321 cdclk_state->cdclk = 133333; in pnv_get_cdclk()
324 cdclk_state->cdclk = 166667; in pnv_get_cdclk()
330 struct intel_cdclk_state *cdclk_state) in i965gm_get_cdclk() argument
340 cdclk_state->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
349 switch (cdclk_state->vco) { in i965gm_get_cdclk()
363 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, in i965gm_get_cdclk()
369 cdclk_state->vco, tmp); in i965gm_get_cdclk()
370 cdclk_state->cdclk = 200000; in i965gm_get_cdclk()
374 struct intel_cdclk_state *cdclk_state) in gm45_get_cdclk() argument
380 cdclk_state->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
386 switch (cdclk_state->vco) { in gm45_get_cdclk()
390 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
393 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
397 cdclk_state->vco, tmp); in gm45_get_cdclk()
398 cdclk_state->cdclk = 222222; in gm45_get_cdclk()
404 struct intel_cdclk_state *cdclk_state) in hsw_get_cdclk() argument
410 cdclk_state->cdclk = 800000; in hsw_get_cdclk()
412 cdclk_state->cdclk = 450000; in hsw_get_cdclk()
414 cdclk_state->cdclk = 450000; in hsw_get_cdclk()
416 cdclk_state->cdclk = 337500; in hsw_get_cdclk()
418 cdclk_state->cdclk = 540000; in hsw_get_cdclk()
461 struct intel_cdclk_state *cdclk_state) in vlv_get_cdclk() argument
465 cdclk_state->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
466 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
468 cdclk_state->vco); in vlv_get_cdclk()
475 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
478 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
519 const struct intel_cdclk_state *cdclk_state) in vlv_set_cdclk() argument
521 int cdclk = cdclk_state->cdclk; in vlv_set_cdclk()
522 u32 val, cmd = cdclk_state->voltage_level; in vlv_set_cdclk()
600 const struct intel_cdclk_state *cdclk_state) in chv_set_cdclk() argument
602 int cdclk = cdclk_state->cdclk; in chv_set_cdclk()
603 u32 val, cmd = cdclk_state->voltage_level; in chv_set_cdclk()
671 struct intel_cdclk_state *cdclk_state) in bdw_get_cdclk() argument
677 cdclk_state->cdclk = 800000; in bdw_get_cdclk()
679 cdclk_state->cdclk = 450000; in bdw_get_cdclk()
681 cdclk_state->cdclk = 450000; in bdw_get_cdclk()
683 cdclk_state->cdclk = 540000; in bdw_get_cdclk()
685 cdclk_state->cdclk = 337500; in bdw_get_cdclk()
687 cdclk_state->cdclk = 675000; in bdw_get_cdclk()
693 cdclk_state->voltage_level = in bdw_get_cdclk()
694 bdw_calc_voltage_level(cdclk_state->cdclk); in bdw_get_cdclk()
698 const struct intel_cdclk_state *cdclk_state) in bdw_set_cdclk() argument
700 int cdclk = cdclk_state->cdclk; in bdw_set_cdclk()
766 cdclk_state->voltage_level); in bdw_set_cdclk()
816 struct intel_cdclk_state *cdclk_state) in skl_dpll0_update() argument
820 cdclk_state->ref = 24000; in skl_dpll0_update()
821 cdclk_state->vco = 0; in skl_dpll0_update()
843 cdclk_state->vco = 8100000; in skl_dpll0_update()
847 cdclk_state->vco = 8640000; in skl_dpll0_update()
856 struct intel_cdclk_state *cdclk_state) in skl_get_cdclk() argument
860 skl_dpll0_update(dev_priv, cdclk_state); in skl_get_cdclk()
862 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in skl_get_cdclk()
864 if (cdclk_state->vco == 0) in skl_get_cdclk()
869 if (cdclk_state->vco == 8640000) { in skl_get_cdclk()
872 cdclk_state->cdclk = 432000; in skl_get_cdclk()
875 cdclk_state->cdclk = 308571; in skl_get_cdclk()
878 cdclk_state->cdclk = 540000; in skl_get_cdclk()
881 cdclk_state->cdclk = 617143; in skl_get_cdclk()
890 cdclk_state->cdclk = 450000; in skl_get_cdclk()
893 cdclk_state->cdclk = 337500; in skl_get_cdclk()
896 cdclk_state->cdclk = 540000; in skl_get_cdclk()
899 cdclk_state->cdclk = 675000; in skl_get_cdclk()
912 cdclk_state->voltage_level = in skl_get_cdclk()
913 skl_calc_voltage_level(cdclk_state->cdclk); in skl_get_cdclk()
988 const struct intel_cdclk_state *cdclk_state) in skl_set_cdclk() argument
990 int cdclk = cdclk_state->cdclk; in skl_set_cdclk()
991 int vco = cdclk_state->vco; in skl_set_cdclk()
1076 cdclk_state->voltage_level); in skl_set_cdclk()
1135 struct intel_cdclk_state cdclk_state; in skl_init_cdclk() local
1151 cdclk_state = dev_priv->cdclk.hw; in skl_init_cdclk()
1153 cdclk_state.vco = dev_priv->skl_preferred_vco_freq; in skl_init_cdclk()
1154 if (cdclk_state.vco == 0) in skl_init_cdclk()
1155 cdclk_state.vco = 8100000; in skl_init_cdclk()
1156 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); in skl_init_cdclk()
1157 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); in skl_init_cdclk()
1159 skl_set_cdclk(dev_priv, &cdclk_state); in skl_init_cdclk()
1171 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in skl_uninit_cdclk() local
1173 cdclk_state.cdclk = cdclk_state.bypass; in skl_uninit_cdclk()
1174 cdclk_state.vco = 0; in skl_uninit_cdclk()
1175 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); in skl_uninit_cdclk()
1177 skl_set_cdclk(dev_priv, &cdclk_state); in skl_uninit_cdclk()
1256 struct intel_cdclk_state *cdclk_state) in bxt_de_pll_update() argument
1260 cdclk_state->ref = 19200; in bxt_de_pll_update()
1261 cdclk_state->vco = 0; in bxt_de_pll_update()
1271 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; in bxt_de_pll_update()
1275 struct intel_cdclk_state *cdclk_state) in bxt_get_cdclk() argument
1280 bxt_de_pll_update(dev_priv, cdclk_state); in bxt_get_cdclk()
1282 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in bxt_get_cdclk()
1284 if (cdclk_state->vco == 0) in bxt_get_cdclk()
1308 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); in bxt_get_cdclk()
1315 cdclk_state->voltage_level = in bxt_get_cdclk()
1316 bxt_calc_voltage_level(cdclk_state->cdclk); in bxt_get_cdclk()
1356 const struct intel_cdclk_state *cdclk_state) in bxt_set_cdclk() argument
1358 int cdclk = cdclk_state->cdclk; in bxt_set_cdclk()
1359 int vco = cdclk_state->vco; in bxt_set_cdclk()
1431 cdclk_state->voltage_level, 150, 2); in bxt_set_cdclk()
1502 struct intel_cdclk_state cdclk_state; in bxt_init_cdclk() local
1510 cdclk_state = dev_priv->cdclk.hw; in bxt_init_cdclk()
1518 cdclk_state.cdclk = glk_calc_cdclk(0); in bxt_init_cdclk()
1519 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); in bxt_init_cdclk()
1521 cdclk_state.cdclk = bxt_calc_cdclk(0); in bxt_init_cdclk()
1522 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); in bxt_init_cdclk()
1524 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); in bxt_init_cdclk()
1526 bxt_set_cdclk(dev_priv, &cdclk_state); in bxt_init_cdclk()
1538 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in bxt_uninit_cdclk() local
1540 cdclk_state.cdclk = cdclk_state.bypass; in bxt_uninit_cdclk()
1541 cdclk_state.vco = 0; in bxt_uninit_cdclk()
1542 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); in bxt_uninit_cdclk()
1544 bxt_set_cdclk(dev_priv, &cdclk_state); in bxt_uninit_cdclk()
1571 struct intel_cdclk_state *cdclk_state) in cnl_cdclk_pll_update() argument
1576 cdclk_state->ref = 24000; in cnl_cdclk_pll_update()
1578 cdclk_state->ref = 19200; in cnl_cdclk_pll_update()
1580 cdclk_state->vco = 0; in cnl_cdclk_pll_update()
1589 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; in cnl_cdclk_pll_update()
1593 struct intel_cdclk_state *cdclk_state) in cnl_get_cdclk() argument
1598 cnl_cdclk_pll_update(dev_priv, cdclk_state); in cnl_get_cdclk()
1600 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in cnl_get_cdclk()
1602 if (cdclk_state->vco == 0) in cnl_get_cdclk()
1619 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); in cnl_get_cdclk()
1626 cdclk_state->voltage_level = in cnl_get_cdclk()
1627 cnl_calc_voltage_level(cdclk_state->cdclk); in cnl_get_cdclk()
1664 const struct intel_cdclk_state *cdclk_state) in cnl_set_cdclk() argument
1666 int cdclk = cdclk_state->cdclk; in cnl_set_cdclk()
1667 int vco = cdclk_state->vco; in cnl_set_cdclk()
1715 cdclk_state->voltage_level); in cnl_set_cdclk()
1724 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; in cnl_set_cdclk()
1848 const struct intel_cdclk_state *cdclk_state) in icl_set_cdclk() argument
1850 unsigned int cdclk = cdclk_state->cdclk; in icl_set_cdclk()
1851 unsigned int vco = cdclk_state->vco; in icl_set_cdclk()
1878 cdclk_state->voltage_level); in icl_set_cdclk()
1887 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; in icl_set_cdclk()
1910 struct intel_cdclk_state *cdclk_state) in icl_get_cdclk() argument
1914 cdclk_state->bypass = 50000; in icl_get_cdclk()
1922 cdclk_state->ref = 24000; in icl_get_cdclk()
1925 cdclk_state->ref = 19200; in icl_get_cdclk()
1928 cdclk_state->ref = 38400; in icl_get_cdclk()
1939 cdclk_state->vco = 0; in icl_get_cdclk()
1940 cdclk_state->cdclk = cdclk_state->bypass; in icl_get_cdclk()
1944 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; in icl_get_cdclk()
1949 cdclk_state->cdclk = cdclk_state->vco / 2; in icl_get_cdclk()
1956 cdclk_state->voltage_level = in icl_get_cdclk()
1957 icl_calc_voltage_level(cdclk_state->cdclk); in icl_get_cdclk()
2015 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in icl_uninit_cdclk() local
2017 cdclk_state.cdclk = cdclk_state.bypass; in icl_uninit_cdclk()
2018 cdclk_state.vco = 0; in icl_uninit_cdclk()
2019 cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk); in icl_uninit_cdclk()
2021 icl_set_cdclk(dev_priv, &cdclk_state); in icl_uninit_cdclk()
2035 struct intel_cdclk_state cdclk_state; in cnl_init_cdclk() local
2043 cdclk_state = dev_priv->cdclk.hw; in cnl_init_cdclk()
2045 cdclk_state.cdclk = cnl_calc_cdclk(0); in cnl_init_cdclk()
2046 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); in cnl_init_cdclk()
2047 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); in cnl_init_cdclk()
2049 cnl_set_cdclk(dev_priv, &cdclk_state); in cnl_init_cdclk()
2061 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in cnl_uninit_cdclk() local
2063 cdclk_state.cdclk = cdclk_state.bypass; in cnl_uninit_cdclk()
2064 cdclk_state.vco = 0; in cnl_uninit_cdclk()
2065 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); in cnl_uninit_cdclk()
2067 cnl_set_cdclk(dev_priv, &cdclk_state); in cnl_uninit_cdclk()
2101 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, in intel_dump_cdclk_state() argument
2105 context, cdclk_state->cdclk, cdclk_state->vco, in intel_dump_cdclk_state()
2106 cdclk_state->ref, cdclk_state->bypass, in intel_dump_cdclk_state()
2107 cdclk_state->voltage_level); in intel_dump_cdclk_state()
2119 const struct intel_cdclk_state *cdclk_state) in intel_set_cdclk() argument
2121 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) in intel_set_cdclk()
2127 intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); in intel_set_cdclk()
2129 dev_priv->display.set_cdclk(dev_priv, cdclk_state); in intel_set_cdclk()
2131 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), in intel_set_cdclk()
2134 intel_dump_cdclk_state(cdclk_state, "[sw state]"); in intel_set_cdclk()