Lines Matching refs:display_mmio_offset
3179 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3180 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3181 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3278 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3279 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3280 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3352 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3493 dev_priv->info.display_mmio_offset + (i) * 4)
4083 dev_priv->info.display_mmio_offset)
4307 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4337 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4419 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4693 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4711 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4723 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4725 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4726 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4730 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4731 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4735 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4736 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4741 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
4764 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4786 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
5410 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5411 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5412 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5413 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5414 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5415 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
5417 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5418 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5419 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5420 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5421 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5422 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5424 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5425 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5426 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5427 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5428 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5429 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5431 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5432 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5433 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5434 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5435 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5436 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5438 #define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
5439 #define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
5440 #define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
5441 #define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
5442 #define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
5443 #define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
5445 #define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5446 #define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5447 #define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5448 #define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5449 #define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5450 #define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5651 dev_priv->info.display_mmio_offset)
5725 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5760 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5771 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5787 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
6102 dev_priv->info.display_mmio_offset)
6207 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6208 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6209 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6213 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6214 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6215 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
6218 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6219 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
6223 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
6228 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6229 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6230 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6231 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6232 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6233 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6234 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6235 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
8707 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
10313 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
10314 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)