Lines Matching refs:VLV_DISPLAY_BASE
976 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
998 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
999 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1251 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
2508 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2610 #define VLV_DISPLAY_BASE 0x180000 macro
2611 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
2614 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2615 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2621 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2624 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2625 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2626 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2627 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2628 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2629 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2630 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2803 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2941 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2945 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2948 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2949 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2950 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3222 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3224 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3235 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3320 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3467 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3470 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3472 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3477 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3484 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
4097 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4098 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4112 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4113 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4119 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4120 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4260 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4409 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4410 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4411 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4617 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
5318 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5319 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5320 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5674 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5695 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5740 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5753 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5798 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5805 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5814 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5817 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5818 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5827 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5836 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5847 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5868 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5891 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5899 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5903 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
6384 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6407 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6408 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6409 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6410 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6411 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6412 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6413 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6414 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6415 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6416 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6418 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6421 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6424 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6426 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6427 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6428 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6429 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6430 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6431 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6432 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6433 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6434 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6435 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6436 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6437 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6438 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6439 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6467 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6731 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
7907 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7908 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7909 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
7911 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7912 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7913 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
7915 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7916 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7917 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8486 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8742 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8743 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8745 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8746 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8748 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8762 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8763 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
9672 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
9673 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
9674 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
9675 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
9676 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
9677 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9678 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9679 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9684 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9685 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9686 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9687 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9688 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9689 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9690 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9691 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9853 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
9854 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
9916 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
9917 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
9923 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)