Lines Matching refs:dev_priv
168 static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv, in gen3_assert_iir_is_zero() argument
184 static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv, in gen2_assert_iir_is_zero() argument
201 gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
208 gen3_assert_iir_is_zero(dev_priv, type##IIR); \
215 gen2_assert_iir_is_zero(dev_priv, type##IIR); \
221 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
222 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
226 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update_locked() argument
232 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
253 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update() argument
257 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
258 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); in i915_hotplug_interrupt_update()
259 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
303 void ilk_update_display_irq(struct drm_i915_private *dev_priv, in ilk_update_display_irq() argument
309 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
313 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_display_irq()
316 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
320 if (new_val != dev_priv->irq_mask) { in ilk_update_display_irq()
321 dev_priv->irq_mask = new_val; in ilk_update_display_irq()
322 I915_WRITE(DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
333 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, in ilk_update_gt_irq() argument
337 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_gt_irq()
341 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_gt_irq()
344 dev_priv->gt_irq_mask &= ~interrupt_mask; in ilk_update_gt_irq()
345 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); in ilk_update_gt_irq()
346 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ilk_update_gt_irq()
349 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen5_enable_gt_irq() argument
351 ilk_update_gt_irq(dev_priv, mask, mask); in gen5_enable_gt_irq()
355 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen5_disable_gt_irq() argument
357 ilk_update_gt_irq(dev_priv, mask, 0); in gen5_disable_gt_irq()
360 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) in gen6_pm_iir() argument
362 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11); in gen6_pm_iir()
364 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
367 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) in gen6_pm_imr() argument
369 if (INTEL_GEN(dev_priv) >= 11) in gen6_pm_imr()
371 else if (INTEL_GEN(dev_priv) >= 8) in gen6_pm_imr()
377 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) in gen6_pm_ier() argument
379 if (INTEL_GEN(dev_priv) >= 11) in gen6_pm_ier()
381 else if (INTEL_GEN(dev_priv) >= 8) in gen6_pm_ier()
393 static void snb_update_pm_irq(struct drm_i915_private *dev_priv, in snb_update_pm_irq() argument
401 lockdep_assert_held(&dev_priv->irq_lock); in snb_update_pm_irq()
403 new_val = dev_priv->pm_imr; in snb_update_pm_irq()
407 if (new_val != dev_priv->pm_imr) { in snb_update_pm_irq()
408 dev_priv->pm_imr = new_val; in snb_update_pm_irq()
409 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr); in snb_update_pm_irq()
410 POSTING_READ(gen6_pm_imr(dev_priv)); in snb_update_pm_irq()
414 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) in gen6_unmask_pm_irq() argument
416 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in gen6_unmask_pm_irq()
419 snb_update_pm_irq(dev_priv, mask, mask); in gen6_unmask_pm_irq()
422 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) in __gen6_mask_pm_irq() argument
424 snb_update_pm_irq(dev_priv, mask, 0); in __gen6_mask_pm_irq()
427 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) in gen6_mask_pm_irq() argument
429 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in gen6_mask_pm_irq()
432 __gen6_mask_pm_irq(dev_priv, mask); in gen6_mask_pm_irq()
435 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) in gen6_reset_pm_iir() argument
437 i915_reg_t reg = gen6_pm_iir(dev_priv); in gen6_reset_pm_iir()
439 lockdep_assert_held(&dev_priv->irq_lock); in gen6_reset_pm_iir()
446 static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) in gen6_enable_pm_irq() argument
448 lockdep_assert_held(&dev_priv->irq_lock); in gen6_enable_pm_irq()
450 dev_priv->pm_ier |= enable_mask; in gen6_enable_pm_irq()
451 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); in gen6_enable_pm_irq()
452 gen6_unmask_pm_irq(dev_priv, enable_mask); in gen6_enable_pm_irq()
456 static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) in gen6_disable_pm_irq() argument
458 lockdep_assert_held(&dev_priv->irq_lock); in gen6_disable_pm_irq()
460 dev_priv->pm_ier &= ~disable_mask; in gen6_disable_pm_irq()
461 __gen6_mask_pm_irq(dev_priv, disable_mask); in gen6_disable_pm_irq()
462 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); in gen6_disable_pm_irq()
466 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv) in gen11_reset_rps_interrupts() argument
468 spin_lock_irq(&dev_priv->irq_lock); in gen11_reset_rps_interrupts()
470 while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM)) in gen11_reset_rps_interrupts()
473 dev_priv->gt_pm.rps.pm_iir = 0; in gen11_reset_rps_interrupts()
475 spin_unlock_irq(&dev_priv->irq_lock); in gen11_reset_rps_interrupts()
478 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) in gen6_reset_rps_interrupts() argument
480 spin_lock_irq(&dev_priv->irq_lock); in gen6_reset_rps_interrupts()
481 gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events); in gen6_reset_rps_interrupts()
482 dev_priv->gt_pm.rps.pm_iir = 0; in gen6_reset_rps_interrupts()
483 spin_unlock_irq(&dev_priv->irq_lock); in gen6_reset_rps_interrupts()
486 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) in gen6_enable_rps_interrupts() argument
488 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_enable_rps_interrupts()
493 spin_lock_irq(&dev_priv->irq_lock); in gen6_enable_rps_interrupts()
496 if (INTEL_GEN(dev_priv) >= 11) in gen6_enable_rps_interrupts()
497 WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM)); in gen6_enable_rps_interrupts()
499 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
502 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
504 spin_unlock_irq(&dev_priv->irq_lock); in gen6_enable_rps_interrupts()
507 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) in gen6_disable_rps_interrupts() argument
509 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_disable_rps_interrupts()
514 spin_lock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
517 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); in gen6_disable_rps_interrupts()
519 gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_disable_rps_interrupts()
521 spin_unlock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
522 synchronize_irq(dev_priv->drm.irq); in gen6_disable_rps_interrupts()
530 if (INTEL_GEN(dev_priv) >= 11) in gen6_disable_rps_interrupts()
531 gen11_reset_rps_interrupts(dev_priv); in gen6_disable_rps_interrupts()
533 gen6_reset_rps_interrupts(dev_priv); in gen6_disable_rps_interrupts()
536 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) in gen9_reset_guc_interrupts() argument
538 assert_rpm_wakelock_held(dev_priv); in gen9_reset_guc_interrupts()
540 spin_lock_irq(&dev_priv->irq_lock); in gen9_reset_guc_interrupts()
541 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events); in gen9_reset_guc_interrupts()
542 spin_unlock_irq(&dev_priv->irq_lock); in gen9_reset_guc_interrupts()
545 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) in gen9_enable_guc_interrupts() argument
547 assert_rpm_wakelock_held(dev_priv); in gen9_enable_guc_interrupts()
549 spin_lock_irq(&dev_priv->irq_lock); in gen9_enable_guc_interrupts()
550 if (!dev_priv->guc.interrupts_enabled) { in gen9_enable_guc_interrupts()
551 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & in gen9_enable_guc_interrupts()
552 dev_priv->pm_guc_events); in gen9_enable_guc_interrupts()
553 dev_priv->guc.interrupts_enabled = true; in gen9_enable_guc_interrupts()
554 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); in gen9_enable_guc_interrupts()
556 spin_unlock_irq(&dev_priv->irq_lock); in gen9_enable_guc_interrupts()
559 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) in gen9_disable_guc_interrupts() argument
561 assert_rpm_wakelock_held(dev_priv); in gen9_disable_guc_interrupts()
563 spin_lock_irq(&dev_priv->irq_lock); in gen9_disable_guc_interrupts()
564 dev_priv->guc.interrupts_enabled = false; in gen9_disable_guc_interrupts()
566 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); in gen9_disable_guc_interrupts()
568 spin_unlock_irq(&dev_priv->irq_lock); in gen9_disable_guc_interrupts()
569 synchronize_irq(dev_priv->drm.irq); in gen9_disable_guc_interrupts()
571 gen9_reset_guc_interrupts(dev_priv); in gen9_disable_guc_interrupts()
580 static void bdw_update_port_irq(struct drm_i915_private *dev_priv, in bdw_update_port_irq() argument
587 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_port_irq()
591 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
613 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, in bdw_update_pipe_irq() argument
620 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_pipe_irq()
624 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in bdw_update_pipe_irq()
627 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
631 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
632 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
633 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
644 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, in ibx_display_interrupt_update() argument
654 lockdep_assert_held(&dev_priv->irq_lock); in ibx_display_interrupt_update()
656 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ibx_display_interrupt_update()
663 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, in i915_pipestat_enable_mask() argument
666 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
669 lockdep_assert_held(&dev_priv->irq_lock); in i915_pipestat_enable_mask()
671 if (INTEL_GEN(dev_priv) < 5) in i915_pipestat_enable_mask()
704 void i915_enable_pipestat(struct drm_i915_private *dev_priv, in i915_enable_pipestat() argument
714 lockdep_assert_held(&dev_priv->irq_lock); in i915_enable_pipestat()
715 WARN_ON(!intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
717 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
720 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
721 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_enable_pipestat()
727 void i915_disable_pipestat(struct drm_i915_private *dev_priv, in i915_disable_pipestat() argument
737 lockdep_assert_held(&dev_priv->irq_lock); in i915_disable_pipestat()
738 WARN_ON(!intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
740 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
743 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
744 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_disable_pipestat()
754 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) in i915_enable_asle_pipestat() argument
756 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) in i915_enable_asle_pipestat()
759 spin_lock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
761 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
762 if (INTEL_GEN(dev_priv) >= 4) in i915_enable_asle_pipestat()
763 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
766 spin_unlock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
824 struct drm_i915_private *dev_priv = to_i915(dev); in i915_get_vblank_counter() local
845 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
858 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
874 struct drm_i915_private *dev_priv = to_i915(dev); in g4x_get_vblank_counter() local
889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in __intel_get_crtc_scanline_from_timestamp() local
934 struct drm_i915_private *dev_priv = to_i915(dev); in __intel_get_crtc_scanline() local
953 if (IS_GEN2(dev_priv)) in __intel_get_crtc_scanline()
970 if (HAS_DDI(dev_priv) && !position) { in __intel_get_crtc_scanline()
995 struct drm_i915_private *dev_priv = to_i915(dev); in i915_get_crtc_scanoutpos() local
996 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, in i915_get_crtc_scanoutpos()
1025 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
1033 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in i915_get_crtc_scanoutpos()
1080 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
1093 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in i915_get_crtc_scanoutpos()
1106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_get_crtc_scanline() local
1110 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1112 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1117 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) in ironlake_rps_change_irq_handler() argument
1126 new_delay = dev_priv->ips.cur_delay; in ironlake_rps_change_irq_handler()
1136 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) in ironlake_rps_change_irq_handler()
1137 new_delay = dev_priv->ips.cur_delay - 1; in ironlake_rps_change_irq_handler()
1138 if (new_delay < dev_priv->ips.max_delay) in ironlake_rps_change_irq_handler()
1139 new_delay = dev_priv->ips.max_delay; in ironlake_rps_change_irq_handler()
1141 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) in ironlake_rps_change_irq_handler()
1142 new_delay = dev_priv->ips.cur_delay + 1; in ironlake_rps_change_irq_handler()
1143 if (new_delay > dev_priv->ips.min_delay) in ironlake_rps_change_irq_handler()
1144 new_delay = dev_priv->ips.min_delay; in ironlake_rps_change_irq_handler()
1147 if (ironlake_set_drps(dev_priv, new_delay)) in ironlake_rps_change_irq_handler()
1148 dev_priv->ips.cur_delay = new_delay; in ironlake_rps_change_irq_handler()
1225 static void vlv_c0_read(struct drm_i915_private *dev_priv, in vlv_c0_read() argument
1233 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) in gen6_rps_reset_ei() argument
1235 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei)); in gen6_rps_reset_ei()
1238 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) in vlv_wa_c0_ei() argument
1240 struct intel_rps *rps = &dev_priv->gt_pm.rps; in vlv_wa_c0_ei()
1248 vlv_c0_read(dev_priv, &now); in vlv_wa_c0_ei()
1256 time *= dev_priv->czclk_freq; in vlv_wa_c0_ei()
1280 struct drm_i915_private *dev_priv = in gen6_pm_rps_work() local
1282 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_pm_rps_work()
1287 spin_lock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1292 spin_unlock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1295 WARN_ON(pm_iir & ~dev_priv->pm_rps_events); in gen6_pm_rps_work()
1296 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) in gen6_pm_rps_work()
1299 mutex_lock(&dev_priv->pcu_lock); in gen6_pm_rps_work()
1301 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); in gen6_pm_rps_work()
1316 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; in gen6_pm_rps_work()
1332 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; in gen6_pm_rps_work()
1348 if (intel_set_rps(dev_priv, new_delay)) { in gen6_pm_rps_work()
1353 mutex_unlock(&dev_priv->pcu_lock); in gen6_pm_rps_work()
1357 spin_lock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1359 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_pm_rps_work()
1360 spin_unlock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1375 struct drm_i915_private *dev_priv = in ivybridge_parity_work() local
1376 container_of(work, typeof(*dev_priv), l3_parity.error_work); in ivybridge_parity_work()
1386 mutex_lock(&dev_priv->drm.struct_mutex); in ivybridge_parity_work()
1389 if (WARN_ON(!dev_priv->l3_parity.which_slice)) in ivybridge_parity_work()
1396 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivybridge_parity_work()
1400 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) in ivybridge_parity_work()
1403 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivybridge_parity_work()
1422 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, in ivybridge_parity_work()
1437 WARN_ON(dev_priv->l3_parity.which_slice); in ivybridge_parity_work()
1438 spin_lock_irq(&dev_priv->irq_lock); in ivybridge_parity_work()
1439 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); in ivybridge_parity_work()
1440 spin_unlock_irq(&dev_priv->irq_lock); in ivybridge_parity_work()
1442 mutex_unlock(&dev_priv->drm.struct_mutex); in ivybridge_parity_work()
1445 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, in ivybridge_parity_error_irq_handler() argument
1448 if (!HAS_L3_DPF(dev_priv)) in ivybridge_parity_error_irq_handler()
1451 spin_lock(&dev_priv->irq_lock); in ivybridge_parity_error_irq_handler()
1452 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); in ivybridge_parity_error_irq_handler()
1453 spin_unlock(&dev_priv->irq_lock); in ivybridge_parity_error_irq_handler()
1455 iir &= GT_PARITY_ERROR(dev_priv); in ivybridge_parity_error_irq_handler()
1457 dev_priv->l3_parity.which_slice |= 1 << 1; in ivybridge_parity_error_irq_handler()
1460 dev_priv->l3_parity.which_slice |= 1 << 0; in ivybridge_parity_error_irq_handler()
1462 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); in ivybridge_parity_error_irq_handler()
1465 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, in ilk_gt_irq_handler() argument
1469 notify_ring(dev_priv->engine[RCS]); in ilk_gt_irq_handler()
1471 notify_ring(dev_priv->engine[VCS]); in ilk_gt_irq_handler()
1474 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, in snb_gt_irq_handler() argument
1478 notify_ring(dev_priv->engine[RCS]); in snb_gt_irq_handler()
1480 notify_ring(dev_priv->engine[VCS]); in snb_gt_irq_handler()
1482 notify_ring(dev_priv->engine[BCS]); in snb_gt_irq_handler()
1489 if (gt_iir & GT_PARITY_ERROR(dev_priv)) in snb_gt_irq_handler()
1490 ivybridge_parity_error_irq_handler(dev_priv, gt_iir); in snb_gt_irq_handler()
1708 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, in intel_get_hpd_pins() argument
1731 static void gmbus_irq_handler(struct drm_i915_private *dev_priv) in gmbus_irq_handler() argument
1733 wake_up_all(&dev_priv->gmbus_wait_queue); in gmbus_irq_handler()
1736 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) in dp_aux_irq_handler() argument
1738 wake_up_all(&dev_priv->gmbus_wait_queue); in dp_aux_irq_handler()
1742 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in display_pipe_crc_irq_handler() argument
1748 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; in display_pipe_crc_irq_handler()
1749 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in display_pipe_crc_irq_handler()
1762 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
1780 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in display_pipe_crc_irq_handler() argument
1788 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in hsw_pipe_crc_irq_handler() argument
1791 display_pipe_crc_irq_handler(dev_priv, pipe, in hsw_pipe_crc_irq_handler()
1796 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in ivb_pipe_crc_irq_handler() argument
1799 display_pipe_crc_irq_handler(dev_priv, pipe, in ivb_pipe_crc_irq_handler()
1807 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in i9xx_pipe_crc_irq_handler() argument
1812 if (INTEL_GEN(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
1817 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1822 display_pipe_crc_irq_handler(dev_priv, pipe, in i9xx_pipe_crc_irq_handler()
1832 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) in gen6_rps_irq_handler() argument
1834 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_irq_handler()
1836 if (pm_iir & dev_priv->pm_rps_events) { in gen6_rps_irq_handler()
1837 spin_lock(&dev_priv->irq_lock); in gen6_rps_irq_handler()
1838 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); in gen6_rps_irq_handler()
1840 rps->pm_iir |= pm_iir & dev_priv->pm_rps_events; in gen6_rps_irq_handler()
1843 spin_unlock(&dev_priv->irq_lock); in gen6_rps_irq_handler()
1846 if (INTEL_GEN(dev_priv) >= 8) in gen6_rps_irq_handler()
1849 if (HAS_VEBOX(dev_priv)) { in gen6_rps_irq_handler()
1851 notify_ring(dev_priv->engine[VECS]); in gen6_rps_irq_handler()
1858 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) in gen9_guc_irq_handler() argument
1861 intel_guc_to_host_event_handler(&dev_priv->guc); in gen9_guc_irq_handler()
1864 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) in i9xx_pipestat_irq_reset() argument
1868 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_reset()
1873 dev_priv->pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
1877 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, in i9xx_pipestat_irq_ack() argument
1882 spin_lock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1884 if (!dev_priv->display_irqs_enabled) { in i9xx_pipestat_irq_ack()
1885 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1889 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_ack()
1916 status_mask |= dev_priv->pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
1923 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_pipestat_irq_ack()
1939 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1942 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, in i8xx_pipestat_irq_handler() argument
1947 for_each_pipe(dev_priv, pipe) { in i8xx_pipestat_irq_handler()
1949 drm_handle_vblank(&dev_priv->drm, pipe); in i8xx_pipestat_irq_handler()
1952 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
1955 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
1959 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, in i915_pipestat_irq_handler() argument
1965 for_each_pipe(dev_priv, pipe) { in i915_pipestat_irq_handler()
1967 drm_handle_vblank(&dev_priv->drm, pipe); in i915_pipestat_irq_handler()
1973 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
1976 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
1980 intel_opregion_asle_intr(dev_priv); in i915_pipestat_irq_handler()
1983 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, in i965_pipestat_irq_handler() argument
1989 for_each_pipe(dev_priv, pipe) { in i965_pipestat_irq_handler()
1991 drm_handle_vblank(&dev_priv->drm, pipe); in i965_pipestat_irq_handler()
1997 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
2000 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
2004 intel_opregion_asle_intr(dev_priv); in i965_pipestat_irq_handler()
2007 gmbus_irq_handler(dev_priv); in i965_pipestat_irq_handler()
2010 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, in valleyview_pipestat_irq_handler() argument
2015 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
2017 drm_handle_vblank(&dev_priv->drm, pipe); in valleyview_pipestat_irq_handler()
2020 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
2023 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
2027 gmbus_irq_handler(dev_priv); in valleyview_pipestat_irq_handler()
2030 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) in i9xx_hpd_irq_ack() argument
2035 if (IS_G4X(dev_priv) || in i9xx_hpd_irq_ack()
2036 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
2068 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, in i9xx_hpd_irq_handler() argument
2073 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_hpd_irq_handler()
2074 IS_CHERRYVIEW(dev_priv)) { in i9xx_hpd_irq_handler()
2078 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
2083 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
2087 dp_aux_irq_handler(dev_priv); in i9xx_hpd_irq_handler()
2092 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
2096 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
2104 struct drm_i915_private *dev_priv = to_i915(dev); in valleyview_irq_handler() local
2107 if (!intel_irqs_enabled(dev_priv)) in valleyview_irq_handler()
2111 disable_rpm_wakeref_asserts(dev_priv); in valleyview_irq_handler()
2151 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in valleyview_irq_handler()
2155 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in valleyview_irq_handler()
2159 intel_lpe_audio_irq_handler(dev_priv); in valleyview_irq_handler()
2172 snb_gt_irq_handler(dev_priv, gt_iir); in valleyview_irq_handler()
2174 gen6_rps_irq_handler(dev_priv, pm_iir); in valleyview_irq_handler()
2177 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in valleyview_irq_handler()
2179 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); in valleyview_irq_handler()
2182 enable_rpm_wakeref_asserts(dev_priv); in valleyview_irq_handler()
2190 struct drm_i915_private *dev_priv = to_i915(dev); in cherryview_irq_handler() local
2193 if (!intel_irqs_enabled(dev_priv)) in cherryview_irq_handler()
2197 disable_rpm_wakeref_asserts(dev_priv); in cherryview_irq_handler()
2231 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); in cherryview_irq_handler()
2234 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in cherryview_irq_handler()
2238 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in cherryview_irq_handler()
2243 intel_lpe_audio_irq_handler(dev_priv); in cherryview_irq_handler()
2255 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir); in cherryview_irq_handler()
2258 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in cherryview_irq_handler()
2260 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); in cherryview_irq_handler()
2263 enable_rpm_wakeref_asserts(dev_priv); in cherryview_irq_handler()
2268 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, in ibx_hpd_irq_handler() argument
2293 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, in ibx_hpd_irq_handler()
2297 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in ibx_hpd_irq_handler()
2300 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in ibx_irq_handler() argument
2305 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); in ibx_irq_handler()
2315 dp_aux_irq_handler(dev_priv); in ibx_irq_handler()
2318 gmbus_irq_handler(dev_priv); in ibx_irq_handler()
2330 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
2342 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
2345 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
2348 static void ivb_err_int_handler(struct drm_i915_private *dev_priv) in ivb_err_int_handler() argument
2356 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
2358 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
2361 if (IS_IVYBRIDGE(dev_priv)) in ivb_err_int_handler()
2362 ivb_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
2364 hsw_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
2371 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) in cpt_serr_int_handler() argument
2379 for_each_pipe(dev_priv, pipe) in cpt_serr_int_handler()
2381 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); in cpt_serr_int_handler()
2386 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in cpt_irq_handler() argument
2391 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); in cpt_irq_handler()
2401 dp_aux_irq_handler(dev_priv); in cpt_irq_handler()
2404 gmbus_irq_handler(dev_priv); in cpt_irq_handler()
2413 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
2419 cpt_serr_int_handler(dev_priv); in cpt_irq_handler()
2422 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in icp_irq_handler() argument
2434 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in icp_irq_handler()
2446 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in icp_irq_handler()
2453 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in icp_irq_handler()
2456 gmbus_irq_handler(dev_priv); in icp_irq_handler()
2459 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in spt_irq_handler() argument
2472 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in spt_irq_handler()
2483 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in spt_irq_handler()
2489 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in spt_irq_handler()
2492 gmbus_irq_handler(dev_priv); in spt_irq_handler()
2495 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, in ilk_hpd_irq_handler() argument
2504 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, in ilk_hpd_irq_handler()
2508 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in ilk_hpd_irq_handler()
2511 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, in ilk_display_irq_handler() argument
2518 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); in ilk_display_irq_handler()
2521 dp_aux_irq_handler(dev_priv); in ilk_display_irq_handler()
2524 intel_opregion_asle_intr(dev_priv); in ilk_display_irq_handler()
2529 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
2531 drm_handle_vblank(&dev_priv->drm, pipe); in ilk_display_irq_handler()
2534 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2537 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2544 if (HAS_PCH_CPT(dev_priv)) in ilk_display_irq_handler()
2545 cpt_irq_handler(dev_priv, pch_iir); in ilk_display_irq_handler()
2547 ibx_irq_handler(dev_priv, pch_iir); in ilk_display_irq_handler()
2553 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) in ilk_display_irq_handler()
2554 ironlake_rps_change_irq_handler(dev_priv); in ilk_display_irq_handler()
2557 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, in ivb_display_irq_handler() argument
2564 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); in ivb_display_irq_handler()
2567 ivb_err_int_handler(dev_priv); in ivb_display_irq_handler()
2572 intel_psr_irq_handler(dev_priv, psr_iir); in ivb_display_irq_handler()
2577 dp_aux_irq_handler(dev_priv); in ivb_display_irq_handler()
2580 intel_opregion_asle_intr(dev_priv); in ivb_display_irq_handler()
2582 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2584 drm_handle_vblank(&dev_priv->drm, pipe); in ivb_display_irq_handler()
2588 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { in ivb_display_irq_handler()
2591 cpt_irq_handler(dev_priv, pch_iir); in ivb_display_irq_handler()
2609 struct drm_i915_private *dev_priv = to_i915(dev); in ironlake_irq_handler() local
2613 if (!intel_irqs_enabled(dev_priv)) in ironlake_irq_handler()
2617 disable_rpm_wakeref_asserts(dev_priv); in ironlake_irq_handler()
2628 if (!HAS_PCH_NOP(dev_priv)) { in ironlake_irq_handler()
2639 if (INTEL_GEN(dev_priv) >= 6) in ironlake_irq_handler()
2640 snb_gt_irq_handler(dev_priv, gt_iir); in ironlake_irq_handler()
2642 ilk_gt_irq_handler(dev_priv, gt_iir); in ironlake_irq_handler()
2649 if (INTEL_GEN(dev_priv) >= 7) in ironlake_irq_handler()
2650 ivb_display_irq_handler(dev_priv, de_iir); in ironlake_irq_handler()
2652 ilk_display_irq_handler(dev_priv, de_iir); in ironlake_irq_handler()
2655 if (INTEL_GEN(dev_priv) >= 6) { in ironlake_irq_handler()
2660 gen6_rps_irq_handler(dev_priv, pm_iir); in ironlake_irq_handler()
2665 if (!HAS_PCH_NOP(dev_priv)) in ironlake_irq_handler()
2669 enable_rpm_wakeref_asserts(dev_priv); in ironlake_irq_handler()
2674 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, in bxt_hpd_irq_handler() argument
2683 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, in bxt_hpd_irq_handler()
2687 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in bxt_hpd_irq_handler()
2690 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) in gen11_hpd_irq_handler() argument
2702 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, in gen11_hpd_irq_handler()
2713 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, in gen11_hpd_irq_handler()
2719 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in gen11_hpd_irq_handler()
2725 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) in gen8_de_irq_handler() argument
2740 intel_opregion_asle_intr(dev_priv); in gen8_de_irq_handler()
2747 intel_psr_irq_handler(dev_priv, psr_iir); in gen8_de_irq_handler()
2759 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { in gen8_de_irq_handler()
2764 gen11_hpd_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2780 if (INTEL_GEN(dev_priv) >= 9) in gen8_de_irq_handler()
2785 if (INTEL_GEN(dev_priv) >= 11) in gen8_de_irq_handler()
2788 if (IS_CNL_WITH_PORT_F(dev_priv) || in gen8_de_irq_handler()
2789 INTEL_GEN(dev_priv) >= 11) in gen8_de_irq_handler()
2793 dp_aux_irq_handler(dev_priv); in gen8_de_irq_handler()
2797 if (IS_GEN9_LP(dev_priv)) { in gen8_de_irq_handler()
2800 bxt_hpd_irq_handler(dev_priv, tmp_mask, in gen8_de_irq_handler()
2804 } else if (IS_BROADWELL(dev_priv)) { in gen8_de_irq_handler()
2807 ilk_hpd_irq_handler(dev_priv, in gen8_de_irq_handler()
2813 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { in gen8_de_irq_handler()
2814 gmbus_irq_handler(dev_priv); in gen8_de_irq_handler()
2825 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_handler()
2841 drm_handle_vblank(&dev_priv->drm, pipe); in gen8_de_irq_handler()
2844 hsw_pipe_crc_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
2847 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
2850 if (INTEL_GEN(dev_priv) >= 9) in gen8_de_irq_handler()
2861 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && in gen8_de_irq_handler()
2873 if (HAS_PCH_ICP(dev_priv)) in gen8_de_irq_handler()
2874 icp_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2875 else if (HAS_PCH_SPT(dev_priv) || in gen8_de_irq_handler()
2876 HAS_PCH_KBP(dev_priv) || in gen8_de_irq_handler()
2877 HAS_PCH_CNP(dev_priv)) in gen8_de_irq_handler()
2878 spt_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2880 cpt_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2895 struct drm_i915_private *dev_priv = to_i915(arg); in gen8_irq_handler() local
2899 if (!intel_irqs_enabled(dev_priv)) in gen8_irq_handler()
2910 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); in gen8_irq_handler()
2914 disable_rpm_wakeref_asserts(dev_priv); in gen8_irq_handler()
2915 gen8_de_irq_handler(dev_priv, master_ctl); in gen8_irq_handler()
2916 enable_rpm_wakeref_asserts(dev_priv); in gen8_irq_handler()
2921 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir); in gen8_irq_handler()
3095 gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl) in gen11_gu_misc_irq_ack() argument
3097 void __iomem * const regs = dev_priv->regs; in gen11_gu_misc_irq_ack()
3111 gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir) in gen11_gu_misc_irq_handler() argument
3114 intel_opregion_asle_intr(dev_priv); in gen11_gu_misc_irq_handler()
3161 static void i915_reset_device(struct drm_i915_private *dev_priv, in i915_reset_device() argument
3165 struct i915_gpu_error *error = &dev_priv->gpu_error; in i915_reset_device()
3166 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; in i915_reset_device()
3178 i915_wedge_on_timeout(&w, dev_priv, 5*HZ) { in i915_reset_device()
3179 intel_prepare_reset(dev_priv); in i915_reset_device()
3193 if (mutex_trylock(&dev_priv->drm.struct_mutex)) { in i915_reset_device()
3194 i915_reset(dev_priv, engine_mask, reason); in i915_reset_device()
3195 mutex_unlock(&dev_priv->drm.struct_mutex); in i915_reset_device()
3205 intel_finish_reset(dev_priv); in i915_reset_device()
3212 static void i915_clear_error_registers(struct drm_i915_private *dev_priv) in i915_clear_error_registers() argument
3216 if (!IS_GEN2(dev_priv)) in i915_clear_error_registers()
3219 if (INTEL_GEN(dev_priv) < 4) in i915_clear_error_registers()
3250 void i915_handle_error(struct drm_i915_private *dev_priv, in i915_handle_error() argument
3277 intel_runtime_pm_get(dev_priv); in i915_handle_error()
3279 engine_mask &= INTEL_INFO(dev_priv)->ring_mask; in i915_handle_error()
3282 i915_capture_error_state(dev_priv, engine_mask, msg); in i915_handle_error()
3283 i915_clear_error_registers(dev_priv); in i915_handle_error()
3290 if (intel_has_reset_engine(dev_priv)) { in i915_handle_error()
3291 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { in i915_handle_error()
3294 &dev_priv->gpu_error.flags)) in i915_handle_error()
3301 &dev_priv->gpu_error.flags); in i915_handle_error()
3302 wake_up_bit(&dev_priv->gpu_error.flags, in i915_handle_error()
3311 if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) { in i915_handle_error()
3312 wait_event(dev_priv->gpu_error.reset_queue, in i915_handle_error()
3314 &dev_priv->gpu_error.flags)); in i915_handle_error()
3319 for_each_engine(engine, dev_priv, tmp) { in i915_handle_error()
3321 &dev_priv->gpu_error.flags)) in i915_handle_error()
3322 wait_on_bit(&dev_priv->gpu_error.flags, in i915_handle_error()
3327 i915_reset_device(dev_priv, engine_mask, msg); in i915_handle_error()
3329 for_each_engine(engine, dev_priv, tmp) { in i915_handle_error()
3331 &dev_priv->gpu_error.flags); in i915_handle_error()
3334 clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags); in i915_handle_error()
3335 wake_up_all(&dev_priv->gpu_error.reset_queue); in i915_handle_error()
3338 intel_runtime_pm_put(dev_priv); in i915_handle_error()
3346 struct drm_i915_private *dev_priv = to_i915(dev); in i8xx_enable_vblank() local
3349 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
3350 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_enable_vblank()
3351 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
3358 struct drm_i915_private *dev_priv = to_i915(dev); in i965_enable_vblank() local
3361 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
3362 i915_enable_pipestat(dev_priv, pipe, in i965_enable_vblank()
3364 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
3371 struct drm_i915_private *dev_priv = to_i915(dev); in ironlake_enable_vblank() local
3373 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? in ironlake_enable_vblank()
3376 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ironlake_enable_vblank()
3377 ilk_enable_display_irq(dev_priv, bit); in ironlake_enable_vblank()
3378 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ironlake_enable_vblank()
3383 if (HAS_PSR(dev_priv)) in ironlake_enable_vblank()
3391 struct drm_i915_private *dev_priv = to_i915(dev); in gen8_enable_vblank() local
3394 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in gen8_enable_vblank()
3395 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in gen8_enable_vblank()
3396 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in gen8_enable_vblank()
3401 if (HAS_PSR(dev_priv)) in gen8_enable_vblank()
3412 struct drm_i915_private *dev_priv = to_i915(dev); in i8xx_disable_vblank() local
3415 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
3416 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_disable_vblank()
3417 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
3422 struct drm_i915_private *dev_priv = to_i915(dev); in i965_disable_vblank() local
3425 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
3426 i915_disable_pipestat(dev_priv, pipe, in i965_disable_vblank()
3428 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
3433 struct drm_i915_private *dev_priv = to_i915(dev); in ironlake_disable_vblank() local
3435 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? in ironlake_disable_vblank()
3438 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ironlake_disable_vblank()
3439 ilk_disable_display_irq(dev_priv, bit); in ironlake_disable_vblank()
3440 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ironlake_disable_vblank()
3445 struct drm_i915_private *dev_priv = to_i915(dev); in gen8_disable_vblank() local
3448 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in gen8_disable_vblank()
3449 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in gen8_disable_vblank()
3450 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in gen8_disable_vblank()
3453 static void ibx_irq_reset(struct drm_i915_private *dev_priv) in ibx_irq_reset() argument
3455 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_reset()
3460 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
3474 struct drm_i915_private *dev_priv = to_i915(dev); in ibx_irq_pre_postinstall() local
3476 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_pre_postinstall()
3484 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) in gen5_gt_irq_reset() argument
3487 if (INTEL_GEN(dev_priv) >= 6) in gen5_gt_irq_reset()
3491 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) in vlv_display_irq_reset() argument
3493 if (IS_CHERRYVIEW(dev_priv)) in vlv_display_irq_reset()
3498 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); in vlv_display_irq_reset()
3501 i9xx_pipestat_irq_reset(dev_priv); in vlv_display_irq_reset()
3504 dev_priv->irq_mask = ~0u; in vlv_display_irq_reset()
3507 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) in vlv_display_irq_postinstall() argument
3515 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3516 for_each_pipe(dev_priv, pipe) in vlv_display_irq_postinstall()
3517 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in vlv_display_irq_postinstall()
3525 if (IS_CHERRYVIEW(dev_priv)) in vlv_display_irq_postinstall()
3529 WARN_ON(dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
3531 dev_priv->irq_mask = ~enable_mask; in vlv_display_irq_postinstall()
3533 GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); in vlv_display_irq_postinstall()
3540 struct drm_i915_private *dev_priv = to_i915(dev); in ironlake_irq_reset() local
3542 if (IS_GEN5(dev_priv)) in ironlake_irq_reset()
3546 if (IS_GEN7(dev_priv)) in ironlake_irq_reset()
3549 if (IS_HASWELL(dev_priv)) { in ironlake_irq_reset()
3554 gen5_gt_irq_reset(dev_priv); in ironlake_irq_reset()
3556 ibx_irq_reset(dev_priv); in ironlake_irq_reset()
3561 struct drm_i915_private *dev_priv = to_i915(dev); in valleyview_irq_reset() local
3566 gen5_gt_irq_reset(dev_priv); in valleyview_irq_reset()
3568 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
3569 if (dev_priv->display_irqs_enabled) in valleyview_irq_reset()
3570 vlv_display_irq_reset(dev_priv); in valleyview_irq_reset()
3571 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
3574 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) in gen8_gt_irq_reset() argument
3584 struct drm_i915_private *dev_priv = to_i915(dev); in gen8_irq_reset() local
3590 gen8_gt_irq_reset(dev_priv); in gen8_irq_reset()
3595 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
3596 if (intel_display_power_is_enabled(dev_priv, in gen8_irq_reset()
3604 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_reset()
3605 ibx_irq_reset(dev_priv); in gen8_irq_reset()
3608 static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) in gen11_gt_irq_reset() argument
3627 struct drm_i915_private *dev_priv = dev->dev_private; in gen11_irq_reset() local
3633 gen11_gt_irq_reset(dev_priv); in gen11_irq_reset()
3637 for_each_pipe(dev_priv, pipe) in gen11_irq_reset()
3638 if (intel_display_power_is_enabled(dev_priv, in gen11_irq_reset()
3648 if (HAS_PCH_ICP(dev_priv)) in gen11_irq_reset()
3652 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, in gen8_irq_power_well_post_enable() argument
3658 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3660 if (!intel_irqs_enabled(dev_priv)) { in gen8_irq_power_well_post_enable()
3661 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3665 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
3667 dev_priv->de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
3668 ~dev_priv->de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
3670 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3673 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, in gen8_irq_power_well_pre_disable() argument
3678 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3680 if (!intel_irqs_enabled(dev_priv)) { in gen8_irq_power_well_pre_disable()
3681 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3685 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
3688 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3691 synchronize_irq(dev_priv->drm.irq); in gen8_irq_power_well_pre_disable()
3696 struct drm_i915_private *dev_priv = to_i915(dev); in cherryview_irq_reset() local
3701 gen8_gt_irq_reset(dev_priv); in cherryview_irq_reset()
3705 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
3706 if (dev_priv->display_irqs_enabled) in cherryview_irq_reset()
3707 vlv_display_irq_reset(dev_priv); in cherryview_irq_reset()
3708 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
3711 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, in intel_hpd_enabled_irqs() argument
3717 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_enabled_irqs()
3718 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) in intel_hpd_enabled_irqs()
3724 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) in ibx_hpd_detection_setup() argument
3744 if (HAS_PCH_LPT_LP(dev_priv)) in ibx_hpd_detection_setup()
3749 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) in ibx_hpd_irq_setup() argument
3753 if (HAS_PCH_IBX(dev_priv)) { in ibx_hpd_irq_setup()
3755 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); in ibx_hpd_irq_setup()
3758 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); in ibx_hpd_irq_setup()
3761 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in ibx_hpd_irq_setup()
3763 ibx_hpd_detection_setup(dev_priv); in ibx_hpd_irq_setup()
3766 static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv) in icp_hpd_detection_setup() argument
3783 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) in icp_hpd_irq_setup() argument
3788 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp); in icp_hpd_irq_setup()
3790 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in icp_hpd_irq_setup()
3792 icp_hpd_detection_setup(dev_priv); in icp_hpd_irq_setup()
3795 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) in gen11_hpd_detection_setup() argument
3814 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) in gen11_hpd_irq_setup() argument
3819 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11); in gen11_hpd_irq_setup()
3827 gen11_hpd_detection_setup(dev_priv); in gen11_hpd_irq_setup()
3829 if (HAS_PCH_ICP(dev_priv)) in gen11_hpd_irq_setup()
3830 icp_hpd_irq_setup(dev_priv); in gen11_hpd_irq_setup()
3833 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) in spt_hpd_detection_setup() argument
3838 if (HAS_PCH_CNP(dev_priv)) { in spt_hpd_detection_setup()
3858 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) in spt_hpd_irq_setup() argument
3863 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); in spt_hpd_irq_setup()
3865 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in spt_hpd_irq_setup()
3867 spt_hpd_detection_setup(dev_priv); in spt_hpd_irq_setup()
3870 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) in ilk_hpd_detection_setup() argument
3886 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) in ilk_hpd_irq_setup() argument
3890 if (INTEL_GEN(dev_priv) >= 8) { in ilk_hpd_irq_setup()
3892 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); in ilk_hpd_irq_setup()
3894 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3895 } else if (INTEL_GEN(dev_priv) >= 7) { in ilk_hpd_irq_setup()
3897 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); in ilk_hpd_irq_setup()
3899 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3902 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); in ilk_hpd_irq_setup()
3904 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3907 ilk_hpd_detection_setup(dev_priv); in ilk_hpd_irq_setup()
3909 ibx_hpd_irq_setup(dev_priv); in ilk_hpd_irq_setup()
3912 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, in __bxt_hpd_detection_setup() argument
3931 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) in __bxt_hpd_detection_setup()
3934 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) in __bxt_hpd_detection_setup()
3937 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) in __bxt_hpd_detection_setup()
3943 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) in bxt_hpd_detection_setup() argument
3945 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); in bxt_hpd_detection_setup()
3948 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) in bxt_hpd_irq_setup() argument
3952 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); in bxt_hpd_irq_setup()
3955 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); in bxt_hpd_irq_setup()
3957 __bxt_hpd_detection_setup(dev_priv, enabled_irqs); in bxt_hpd_irq_setup()
3962 struct drm_i915_private *dev_priv = to_i915(dev); in ibx_irq_postinstall() local
3965 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_postinstall()
3968 if (HAS_PCH_IBX(dev_priv)) in ibx_irq_postinstall()
3970 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_postinstall()
3975 gen3_assert_iir_is_zero(dev_priv, SDEIIR); in ibx_irq_postinstall()
3978 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || in ibx_irq_postinstall()
3979 HAS_PCH_LPT(dev_priv)) in ibx_irq_postinstall()
3980 ibx_hpd_detection_setup(dev_priv); in ibx_irq_postinstall()
3982 spt_hpd_detection_setup(dev_priv); in ibx_irq_postinstall()
3987 struct drm_i915_private *dev_priv = to_i915(dev); in gen5_gt_irq_postinstall() local
3992 dev_priv->gt_irq_mask = ~0; in gen5_gt_irq_postinstall()
3993 if (HAS_L3_DPF(dev_priv)) { in gen5_gt_irq_postinstall()
3995 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv); in gen5_gt_irq_postinstall()
3996 gt_irqs |= GT_PARITY_ERROR(dev_priv); in gen5_gt_irq_postinstall()
4000 if (IS_GEN5(dev_priv)) { in gen5_gt_irq_postinstall()
4006 GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); in gen5_gt_irq_postinstall()
4008 if (INTEL_GEN(dev_priv) >= 6) { in gen5_gt_irq_postinstall()
4013 if (HAS_VEBOX(dev_priv)) { in gen5_gt_irq_postinstall()
4015 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT; in gen5_gt_irq_postinstall()
4018 dev_priv->pm_imr = 0xffffffff; in gen5_gt_irq_postinstall()
4019 GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); in gen5_gt_irq_postinstall()
4025 struct drm_i915_private *dev_priv = to_i915(dev); in ironlake_irq_postinstall() local
4028 if (INTEL_GEN(dev_priv) >= 7) { in ironlake_irq_postinstall()
4043 if (IS_HASWELL(dev_priv)) { in ironlake_irq_postinstall()
4044 gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); in ironlake_irq_postinstall()
4045 intel_psr_irq_control(dev_priv, dev_priv->psr.debug); in ironlake_irq_postinstall()
4049 dev_priv->irq_mask = ~display_mask; in ironlake_irq_postinstall()
4053 GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); in ironlake_irq_postinstall()
4057 ilk_hpd_detection_setup(dev_priv); in ironlake_irq_postinstall()
4061 if (IS_IRONLAKE_M(dev_priv)) { in ironlake_irq_postinstall()
4067 spin_lock_irq(&dev_priv->irq_lock); in ironlake_irq_postinstall()
4068 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); in ironlake_irq_postinstall()
4069 spin_unlock_irq(&dev_priv->irq_lock); in ironlake_irq_postinstall()
4075 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_enable_display_irqs() argument
4077 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_enable_display_irqs()
4079 if (dev_priv->display_irqs_enabled) in valleyview_enable_display_irqs()
4082 dev_priv->display_irqs_enabled = true; in valleyview_enable_display_irqs()
4084 if (intel_irqs_enabled(dev_priv)) { in valleyview_enable_display_irqs()
4085 vlv_display_irq_reset(dev_priv); in valleyview_enable_display_irqs()
4086 vlv_display_irq_postinstall(dev_priv); in valleyview_enable_display_irqs()
4090 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_disable_display_irqs() argument
4092 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_disable_display_irqs()
4094 if (!dev_priv->display_irqs_enabled) in valleyview_disable_display_irqs()
4097 dev_priv->display_irqs_enabled = false; in valleyview_disable_display_irqs()
4099 if (intel_irqs_enabled(dev_priv)) in valleyview_disable_display_irqs()
4100 vlv_display_irq_reset(dev_priv); in valleyview_disable_display_irqs()
4106 struct drm_i915_private *dev_priv = to_i915(dev); in valleyview_irq_postinstall() local
4110 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
4111 if (dev_priv->display_irqs_enabled) in valleyview_irq_postinstall()
4112 vlv_display_irq_postinstall(dev_priv); in valleyview_irq_postinstall()
4113 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
4121 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_gt_irq_postinstall() argument
4138 if (HAS_L3_DPF(dev_priv)) in gen8_gt_irq_postinstall()
4141 dev_priv->pm_ier = 0x0; in gen8_gt_irq_postinstall()
4142 dev_priv->pm_imr = ~dev_priv->pm_ier; in gen8_gt_irq_postinstall()
4149 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); in gen8_gt_irq_postinstall()
4153 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_de_irq_postinstall() argument
4162 if (INTEL_GEN(dev_priv) <= 10) in gen8_de_irq_postinstall()
4165 if (INTEL_GEN(dev_priv) >= 9) { in gen8_de_irq_postinstall()
4169 if (IS_GEN9_LP(dev_priv)) in gen8_de_irq_postinstall()
4175 if (INTEL_GEN(dev_priv) >= 11) in gen8_de_irq_postinstall()
4178 if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11) in gen8_de_irq_postinstall()
4185 if (IS_GEN9_LP(dev_priv)) in gen8_de_irq_postinstall()
4187 else if (IS_BROADWELL(dev_priv)) in gen8_de_irq_postinstall()
4190 gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); in gen8_de_irq_postinstall()
4191 intel_psr_irq_control(dev_priv, dev_priv->psr.debug); in gen8_de_irq_postinstall()
4193 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_postinstall()
4194 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
4196 if (intel_display_power_is_enabled(dev_priv, in gen8_de_irq_postinstall()
4199 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
4206 if (INTEL_GEN(dev_priv) >= 11) { in gen8_de_irq_postinstall()
4212 gen11_hpd_detection_setup(dev_priv); in gen8_de_irq_postinstall()
4213 } else if (IS_GEN9_LP(dev_priv)) { in gen8_de_irq_postinstall()
4214 bxt_hpd_detection_setup(dev_priv); in gen8_de_irq_postinstall()
4215 } else if (IS_BROADWELL(dev_priv)) { in gen8_de_irq_postinstall()
4216 ilk_hpd_detection_setup(dev_priv); in gen8_de_irq_postinstall()
4222 struct drm_i915_private *dev_priv = to_i915(dev); in gen8_irq_postinstall() local
4224 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_postinstall()
4227 gen8_gt_irq_postinstall(dev_priv); in gen8_irq_postinstall()
4228 gen8_de_irq_postinstall(dev_priv); in gen8_irq_postinstall()
4230 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_postinstall()
4239 static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) in gen11_gt_irq_postinstall() argument
4260 dev_priv->pm_ier = 0x0; in gen11_gt_irq_postinstall()
4261 dev_priv->pm_imr = ~dev_priv->pm_ier; in gen11_gt_irq_postinstall()
4268 struct drm_i915_private *dev_priv = to_i915(dev); in icp_irq_postinstall() local
4275 gen3_assert_iir_is_zero(dev_priv, SDEIIR); in icp_irq_postinstall()
4278 icp_hpd_detection_setup(dev_priv); in icp_irq_postinstall()
4283 struct drm_i915_private *dev_priv = dev->dev_private; in gen11_irq_postinstall() local
4286 if (HAS_PCH_ICP(dev_priv)) in gen11_irq_postinstall()
4289 gen11_gt_irq_postinstall(dev_priv); in gen11_irq_postinstall()
4290 gen8_de_irq_postinstall(dev_priv); in gen11_irq_postinstall()
4304 struct drm_i915_private *dev_priv = to_i915(dev); in cherryview_irq_postinstall() local
4306 gen8_gt_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
4308 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
4309 if (dev_priv->display_irqs_enabled) in cherryview_irq_postinstall()
4310 vlv_display_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
4311 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
4321 struct drm_i915_private *dev_priv = to_i915(dev); in i8xx_irq_reset() local
4323 i9xx_pipestat_irq_reset(dev_priv); in i8xx_irq_reset()
4332 struct drm_i915_private *dev_priv = to_i915(dev); in i8xx_irq_postinstall() local
4339 dev_priv->irq_mask = in i8xx_irq_postinstall()
4350 GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask); in i8xx_irq_postinstall()
4354 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
4355 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4356 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4357 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
4362 static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv, in i8xx_error_irq_ack() argument
4391 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, in i8xx_error_irq_handler() argument
4400 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, in i9xx_error_irq_ack() argument
4428 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, in i9xx_error_irq_handler() argument
4440 struct drm_i915_private *dev_priv = to_i915(dev); in i8xx_irq_handler() local
4443 if (!intel_irqs_enabled(dev_priv)) in i8xx_irq_handler()
4447 disable_rpm_wakeref_asserts(dev_priv); in i8xx_irq_handler()
4462 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
4465 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i8xx_irq_handler()
4470 notify_ring(dev_priv->engine[RCS]); in i8xx_irq_handler()
4473 i8xx_error_irq_handler(dev_priv, eir, eir_stuck); in i8xx_irq_handler()
4475 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
4478 enable_rpm_wakeref_asserts(dev_priv); in i8xx_irq_handler()
4485 struct drm_i915_private *dev_priv = to_i915(dev); in i915_irq_reset() local
4487 if (I915_HAS_HOTPLUG(dev_priv)) { in i915_irq_reset()
4488 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i915_irq_reset()
4492 i9xx_pipestat_irq_reset(dev_priv); in i915_irq_reset()
4501 struct drm_i915_private *dev_priv = to_i915(dev); in i915_irq_postinstall() local
4508 dev_priv->irq_mask = in i915_irq_postinstall()
4521 if (I915_HAS_HOTPLUG(dev_priv)) { in i915_irq_postinstall()
4525 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
4528 GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); in i915_irq_postinstall()
4532 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4533 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4534 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4535 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4537 i915_enable_asle_pipestat(dev_priv); in i915_irq_postinstall()
4545 struct drm_i915_private *dev_priv = to_i915(dev); in i915_irq_handler() local
4548 if (!intel_irqs_enabled(dev_priv)) in i915_irq_handler()
4552 disable_rpm_wakeref_asserts(dev_priv); in i915_irq_handler()
4566 if (I915_HAS_HOTPLUG(dev_priv) && in i915_irq_handler()
4568 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in i915_irq_handler()
4572 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i915_irq_handler()
4575 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i915_irq_handler()
4580 notify_ring(dev_priv->engine[RCS]); in i915_irq_handler()
4583 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); in i915_irq_handler()
4586 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in i915_irq_handler()
4588 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i915_irq_handler()
4591 enable_rpm_wakeref_asserts(dev_priv); in i915_irq_handler()
4598 struct drm_i915_private *dev_priv = to_i915(dev); in i965_irq_reset() local
4600 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i965_irq_reset()
4603 i9xx_pipestat_irq_reset(dev_priv); in i965_irq_reset()
4612 struct drm_i915_private *dev_priv = to_i915(dev); in i965_irq_postinstall() local
4620 if (IS_G4X(dev_priv)) { in i965_irq_postinstall()
4632 dev_priv->irq_mask = in i965_irq_postinstall()
4647 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
4650 GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); in i965_irq_postinstall()
4654 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4655 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
4656 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
4657 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
4658 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4660 i915_enable_asle_pipestat(dev_priv); in i965_irq_postinstall()
4665 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) in i915_hpd_irq_setup() argument
4669 lockdep_assert_held(&dev_priv->irq_lock); in i915_hpd_irq_setup()
4673 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); in i915_hpd_irq_setup()
4678 if (IS_G4X(dev_priv)) in i915_hpd_irq_setup()
4683 i915_hotplug_interrupt_update_locked(dev_priv, in i915_hpd_irq_setup()
4693 struct drm_i915_private *dev_priv = to_i915(dev); in i965_irq_handler() local
4696 if (!intel_irqs_enabled(dev_priv)) in i965_irq_handler()
4700 disable_rpm_wakeref_asserts(dev_priv); in i965_irq_handler()
4715 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in i965_irq_handler()
4719 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i965_irq_handler()
4722 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i965_irq_handler()
4727 notify_ring(dev_priv->engine[RCS]); in i965_irq_handler()
4730 notify_ring(dev_priv->engine[VCS]); in i965_irq_handler()
4733 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); in i965_irq_handler()
4736 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in i965_irq_handler()
4738 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i965_irq_handler()
4741 enable_rpm_wakeref_asserts(dev_priv); in i965_irq_handler()
4753 void intel_irq_init(struct drm_i915_private *dev_priv) in intel_irq_init() argument
4755 struct drm_device *dev = &dev_priv->drm; in intel_irq_init()
4756 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_irq_init()
4759 intel_hpd_init_work(dev_priv); in intel_irq_init()
4763 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); in intel_irq_init()
4765 dev_priv->l3_parity.remap_info[i] = NULL; in intel_irq_init()
4767 if (HAS_GUC_SCHED(dev_priv)) in intel_irq_init()
4768 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; in intel_irq_init()
4771 if (IS_VALLEYVIEW(dev_priv)) in intel_irq_init()
4773 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; in intel_irq_init()
4775 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; in intel_irq_init()
4785 if (INTEL_GEN(dev_priv) <= 7) in intel_irq_init()
4788 if (INTEL_GEN(dev_priv) >= 8) in intel_irq_init()
4791 if (IS_GEN2(dev_priv)) { in intel_irq_init()
4794 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in intel_irq_init()
4807 if (!IS_GEN2(dev_priv)) in intel_irq_init()
4816 dev_priv->display_irqs_enabled = true; in intel_irq_init()
4817 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
4818 dev_priv->display_irqs_enabled = false; in intel_irq_init()
4820 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; in intel_irq_init()
4825 if (IS_CHERRYVIEW(dev_priv)) { in intel_irq_init()
4832 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4833 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_irq_init()
4840 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4841 } else if (INTEL_GEN(dev_priv) >= 11) { in intel_irq_init()
4848 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; in intel_irq_init()
4849 } else if (INTEL_GEN(dev_priv) >= 8) { in intel_irq_init()
4856 if (IS_GEN9_LP(dev_priv)) in intel_irq_init()
4857 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; in intel_irq_init()
4858 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || in intel_irq_init()
4859 HAS_PCH_CNP(dev_priv)) in intel_irq_init()
4860 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; in intel_irq_init()
4862 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; in intel_irq_init()
4863 } else if (HAS_PCH_SPLIT(dev_priv)) { in intel_irq_init()
4870 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; in intel_irq_init()
4872 if (IS_GEN2(dev_priv)) { in intel_irq_init()
4879 } else if (IS_GEN3(dev_priv)) { in intel_irq_init()
4894 if (I915_HAS_HOTPLUG(dev_priv)) in intel_irq_init()
4895 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4924 int intel_irq_install(struct drm_i915_private *dev_priv) in intel_irq_install() argument
4931 dev_priv->runtime_pm.irqs_enabled = true; in intel_irq_install()
4933 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq); in intel_irq_install()
4943 void intel_irq_uninstall(struct drm_i915_private *dev_priv) in intel_irq_uninstall() argument
4945 drm_irq_uninstall(&dev_priv->drm); in intel_irq_uninstall()
4946 intel_hpd_cancel_work(dev_priv); in intel_irq_uninstall()
4947 dev_priv->runtime_pm.irqs_enabled = false; in intel_irq_uninstall()
4957 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_disable_interrupts() argument
4959 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm); in intel_runtime_pm_disable_interrupts()
4960 dev_priv->runtime_pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
4961 synchronize_irq(dev_priv->drm.irq); in intel_runtime_pm_disable_interrupts()
4971 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable_interrupts() argument
4973 dev_priv->runtime_pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
4974 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm); in intel_runtime_pm_enable_interrupts()
4975 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm); in intel_runtime_pm_enable_interrupts()