Lines Matching refs:dev_priv
333 struct drm_i915_private *dev_priv; member
408 void (*get_cdclk)(struct drm_i915_private *dev_priv,
410 void (*set_cdclk)(struct drm_i915_private *dev_priv,
412 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
448 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
449 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
664 struct drm_i915_private *dev_priv; member
850 void (*sync_hw)(struct drm_i915_private *dev_priv,
857 void (*enable)(struct drm_i915_private *dev_priv,
863 void (*disable)(struct drm_i915_private *dev_priv,
866 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1419 struct drm_i915_private *dev_priv; member
1473 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1480 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1486 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1503 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1511 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1518 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1523 void (*oa_enable)(struct drm_i915_private *dev_priv);
1528 void (*oa_disable)(struct drm_i915_private *dev_priv);
1546 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
2298 intel_info(const struct drm_i915_private *dev_priv) in intel_info() argument
2300 return &dev_priv->info; in intel_info()
2303 #define INTEL_INFO(dev_priv) intel_info((dev_priv)) argument
2304 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
2306 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) argument
2307 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) argument
2310 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) argument
2326 #define IS_GEN(dev_priv, s, e) \ argument
2327 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2337 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) argument
2339 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) argument
2340 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) argument
2341 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) argument
2342 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) argument
2343 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) argument
2344 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) argument
2345 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) argument
2346 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) argument
2347 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) argument
2348 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) argument
2349 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) argument
2350 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) argument
2351 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) argument
2352 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) argument
2353 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) argument
2354 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) argument
2355 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) argument
2356 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) argument
2357 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) argument
2358 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ argument
2359 (dev_priv)->info.gt == 1)
2360 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) argument
2361 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) argument
2362 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) argument
2363 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) argument
2364 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) argument
2365 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) argument
2366 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) argument
2367 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) argument
2368 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) argument
2369 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) argument
2370 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) argument
2371 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) argument
2372 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ argument
2373 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2374 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ argument
2375 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2376 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2377 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2379 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ argument
2380 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2381 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ argument
2382 (dev_priv)->info.gt == 3)
2383 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ argument
2384 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2385 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ argument
2386 (dev_priv)->info.gt == 3)
2388 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ argument
2389 INTEL_DEVID(dev_priv) == 0x0A1E)
2390 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ argument
2391 INTEL_DEVID(dev_priv) == 0x1913 || \
2392 INTEL_DEVID(dev_priv) == 0x1916 || \
2393 INTEL_DEVID(dev_priv) == 0x1921 || \
2394 INTEL_DEVID(dev_priv) == 0x1926)
2395 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ argument
2396 INTEL_DEVID(dev_priv) == 0x1915 || \
2397 INTEL_DEVID(dev_priv) == 0x191E)
2398 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ argument
2399 INTEL_DEVID(dev_priv) == 0x5913 || \
2400 INTEL_DEVID(dev_priv) == 0x5916 || \
2401 INTEL_DEVID(dev_priv) == 0x5921 || \
2402 INTEL_DEVID(dev_priv) == 0x5926)
2403 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ argument
2404 INTEL_DEVID(dev_priv) == 0x5915 || \
2405 INTEL_DEVID(dev_priv) == 0x591E)
2406 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ argument
2407 (dev_priv)->info.gt == 2)
2408 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ argument
2409 (dev_priv)->info.gt == 3)
2410 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ argument
2411 (dev_priv)->info.gt == 4)
2412 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ argument
2413 (dev_priv)->info.gt == 2)
2414 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ argument
2415 (dev_priv)->info.gt == 3)
2416 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ argument
2417 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2418 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ argument
2419 (dev_priv)->info.gt == 2)
2420 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ argument
2421 (dev_priv)->info.gt == 3)
2422 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ argument
2423 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2444 #define IS_BXT_REVID(dev_priv, since, until) \ argument
2445 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2453 #define IS_KBL_REVID(dev_priv, since, until) \ argument
2454 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2459 #define IS_GLK_REVID(dev_priv, since, until) \ argument
2460 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2484 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) argument
2485 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) argument
2486 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) argument
2487 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) argument
2488 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) argument
2489 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) argument
2490 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) argument
2491 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) argument
2492 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) argument
2493 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) argument
2495 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) argument
2496 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) argument
2497 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) argument
2510 #define HAS_ENGINE(dev_priv, id) \ argument
2511 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2513 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) argument
2514 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) argument
2515 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) argument
2516 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) argument
2518 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) argument
2520 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) argument
2521 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) argument
2522 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) argument
2523 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ argument
2524 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2526 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) argument
2528 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ argument
2529 ((dev_priv)->info.has_logical_ring_contexts)
2530 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ argument
2531 ((dev_priv)->info.has_logical_ring_elsq)
2532 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ argument
2533 ((dev_priv)->info.has_logical_ring_preemption)
2535 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) argument
2537 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) argument
2538 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) argument
2539 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3) argument
2540 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ argument
2542 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2545 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) argument
2546 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ argument
2547 ((dev_priv)->info.overlay_needs_physical)
2550 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) argument
2553 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ argument
2554 (IS_CANNONLAKE(dev_priv) || \
2555 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2557 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) argument
2558 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ argument
2559 IS_GEMINILAKE(dev_priv) || \
2560 IS_KABYLAKE(dev_priv))
2565 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ argument
2566 !(IS_I915G(dev_priv) || \
2567 IS_I915GM(dev_priv)))
2568 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) argument
2569 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) argument
2571 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) argument
2572 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) argument
2573 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) argument
2575 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) argument
2577 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) argument
2579 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) argument
2580 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) argument
2581 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) argument
2583 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) argument
2584 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) argument
2585 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ argument
2587 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) argument
2589 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) argument
2590 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) argument
2592 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) argument
2599 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) argument
2600 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) argument
2601 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) argument
2602 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) argument
2605 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv)) argument
2606 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) argument
2609 #define USES_GUC(dev_priv) intel_uc_is_using_guc() argument
2610 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission() argument
2611 #define USES_HUC(dev_priv) intel_uc_is_using_huc() argument
2613 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) argument
2615 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) argument
2635 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
2636 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
2637 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
2638 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
2639 #define HAS_PCH_CNP_LP(dev_priv) \ argument
2640 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2641 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) argument
2642 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
2643 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) argument
2644 #define HAS_PCH_LPT_LP(dev_priv) \ argument
2645 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2646 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2647 #define HAS_PCH_LPT_H(dev_priv) \ argument
2648 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2649 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2650 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) argument
2651 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) argument
2652 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) argument
2653 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) argument
2655 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) argument
2657 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) argument
2660 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) argument
2661 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ argument
2662 2 : HAS_L3_DPF(dev_priv))
2678 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) in intel_scanout_needs_vtd_wa() argument
2680 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); in intel_scanout_needs_vtd_wa()
2684 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) in intel_ggtt_update_needs_vtd_wa() argument
2686 return IS_BROXTON(dev_priv) && intel_vtd_active(); in intel_ggtt_update_needs_vtd_wa()
2689 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2694 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2697 #define i915_report_error(dev_priv, fmt, ...) \ argument
2698 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2711 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2712 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2720 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2721 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2725 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2726 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2727 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2728 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2729 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2730 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2732 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2733 int intel_engines_init(struct drm_i915_private *dev_priv);
2735 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2738 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2740 void intel_hpd_init(struct drm_i915_private *dev_priv);
2741 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2742 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2743 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2745 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2746 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2749 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) in i915_queue_hangcheck() argument
2763 &dev_priv->gpu_error.hangcheck_work, delay); in i915_queue_hangcheck()
2767 void i915_handle_error(struct drm_i915_private *dev_priv,
2773 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2774 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2775 int intel_irq_install(struct drm_i915_private *dev_priv);
2776 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2778 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) in intel_gvt_active() argument
2780 return dev_priv->gvt; in intel_gvt_active()
2783 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) in intel_vgpu_active() argument
2785 return dev_priv->vgpu.active; in intel_vgpu_active()
2788 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2791 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2795 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2798 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2799 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2800 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2803 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2807 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) in ilk_enable_display_irq() argument
2809 ilk_update_display_irq(dev_priv, bits, bits); in ilk_enable_display_irq()
2812 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) in ilk_disable_display_irq() argument
2814 ilk_update_display_irq(dev_priv, bits, 0); in ilk_disable_display_irq()
2816 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2820 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, in bdw_enable_pipe_irq() argument
2823 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); in bdw_enable_pipe_irq()
2825 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, in bdw_disable_pipe_irq() argument
2828 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); in bdw_disable_pipe_irq()
2830 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2834 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) in ibx_enable_display_interrupt() argument
2836 ibx_display_interrupt_update(dev_priv, bits, bits); in ibx_enable_display_interrupt()
2839 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) in ibx_disable_display_interrupt() argument
2841 ibx_display_interrupt_update(dev_priv, bits, 0); in ibx_disable_display_interrupt()
2877 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2878 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2886 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2887 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2888 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2889 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2890 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2892 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2897 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2899 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2950 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3138 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3139 void i915_gem_reset(struct drm_i915_private *dev_priv,
3142 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3143 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3144 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3150 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3151 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3152 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3153 void i915_gem_fini(struct drm_i915_private *dev_priv);
3154 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3155 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3157 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3158 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3159 void i915_gem_resume(struct drm_i915_private *dev_priv);
3204 i915_reserve_fence(struct drm_i915_private *dev_priv);
3207 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3208 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3210 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3257 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3260 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) in i915_gem_chipset_flush() argument
3263 if (INTEL_GEN(dev_priv) < 6) in i915_gem_chipset_flush()
3268 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3271 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3275 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3277 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3280 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3283 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3290 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3311 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); in i915_gem_object_needs_bit17_swizzle() local
3313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && in i915_gem_object_needs_bit17_swizzle()
3317 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3319 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3324 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3326 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3328 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} in i915_debugfs_register() argument
3331 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} in intel_display_crc_init() argument
3337 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3348 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3349 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3350 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3351 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3354 extern int i915_save_state(struct drm_i915_private *dev_priv);
3355 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3358 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3359 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3362 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3363 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3364 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3365 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3370 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3371 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3372 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3377 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3384 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3387 void intel_bios_init(struct drm_i915_private *dev_priv);
3388 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3390 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3391 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3392 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3393 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3394 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3395 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3396 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3398 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3412 mkwrite_device_info(struct drm_i915_private *dev_priv) in mkwrite_device_info() argument
3414 return (struct intel_device_info *)&dev_priv->info; in mkwrite_device_info()
3423 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3426 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3427 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3428 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3429 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3430 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3433 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3441 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3446 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3450 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3451 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3454 #define sandybridge_pcode_write(dev_priv, mbox, val) \ argument
3455 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3457 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3461 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3462 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3463 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3464 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3465 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3466 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3467 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3468 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3469 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3470 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3471 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3472 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3473 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3474 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3476 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3478 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3479 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3482 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3484 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3487 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3488 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3489 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3491 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3522 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3523 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3524 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3527 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3529 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, in intel_rc6_residency_us() argument
3532 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); in intel_rc6_residency_us()
3535 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3536 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3538 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3539 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3540 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3541 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), f…
3543 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3544 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3545 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3546 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), fal…
3562 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3578 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3581 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3585 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3588 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3629 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3630 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3631 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3639 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) in i915_vgacntrl_reg() argument
3641 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i915_vgacntrl_reg()
3643 else if (INTEL_GEN(dev_priv) >= 5) in i915_vgacntrl_reg()
3777 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);