Lines Matching refs:dev_priv
89 __i915_printk(struct drm_i915_private *dev_priv, const char *level, in __i915_printk() argument
93 struct device *kdev = dev_priv->drm.dev; in __i915_printk()
129 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) in intel_pch_type() argument
134 WARN_ON(!IS_GEN5(dev_priv)); in intel_pch_type()
138 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
142 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
147 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
148 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
152 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
153 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
157 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
158 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
163 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
164 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
169 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); in intel_pch_type()
173 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); in intel_pch_type()
177 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && in intel_pch_type()
178 !IS_COFFEELAKE(dev_priv)); in intel_pch_type()
182 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); in intel_pch_type()
186 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); in intel_pch_type()
190 WARN_ON(!IS_ICELAKE(dev_priv)); in intel_pch_type()
208 intel_virt_detect_pch(const struct drm_i915_private *dev_priv) in intel_virt_detect_pch() argument
219 if (IS_GEN5(dev_priv)) in intel_virt_detect_pch()
221 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) in intel_virt_detect_pch()
223 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) in intel_virt_detect_pch()
225 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_virt_detect_pch()
227 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) in intel_virt_detect_pch()
229 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) in intel_virt_detect_pch()
231 else if (IS_ICELAKE(dev_priv)) in intel_virt_detect_pch()
242 static void intel_detect_pch(struct drm_i915_private *dev_priv) in intel_detect_pch() argument
266 pch_type = intel_pch_type(dev_priv, id); in intel_detect_pch()
268 dev_priv->pch_type = pch_type; in intel_detect_pch()
269 dev_priv->pch_id = id; in intel_detect_pch()
273 id = intel_virt_detect_pch(dev_priv); in intel_detect_pch()
274 pch_type = intel_pch_type(dev_priv, id); in intel_detect_pch()
280 dev_priv->pch_type = pch_type; in intel_detect_pch()
281 dev_priv->pch_id = id; in intel_detect_pch()
290 if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) { in intel_detect_pch()
292 dev_priv->pch_type = PCH_NOP; in intel_detect_pch()
293 dev_priv->pch_id = 0; in intel_detect_pch()
305 struct drm_i915_private *dev_priv = to_i915(dev); in i915_getparam_ioctl() local
306 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_getparam_ioctl()
324 value = dev_priv->num_fence_regs; in i915_getparam_ioctl()
327 value = dev_priv->overlay ? 1 : 0; in i915_getparam_ioctl()
330 value = !!dev_priv->engine[VCS]; in i915_getparam_ioctl()
333 value = !!dev_priv->engine[BCS]; in i915_getparam_ioctl()
336 value = !!dev_priv->engine[VECS]; in i915_getparam_ioctl()
339 value = !!dev_priv->engine[VCS2]; in i915_getparam_ioctl()
342 value = HAS_LLC(dev_priv); in i915_getparam_ioctl()
345 value = HAS_WT(dev_priv); in i915_getparam_ioctl()
348 value = USES_PPGTT(dev_priv); in i915_getparam_ioctl()
351 value = HAS_LEGACY_SEMAPHORES(dev_priv); in i915_getparam_ioctl()
357 value = i915_cmd_parser_get_version(dev_priv); in i915_getparam_ioctl()
360 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); in i915_getparam_ioctl()
365 value = INTEL_INFO(dev_priv)->sseu.eu_total; in i915_getparam_ioctl()
371 intel_has_gpu_reset(dev_priv); in i915_getparam_ioctl()
372 if (value && intel_has_reset_engine(dev_priv)) in i915_getparam_ioctl()
376 value = HAS_RESOURCE_STREAMER(dev_priv); in i915_getparam_ioctl()
379 value = HAS_POOLED_EU(dev_priv); in i915_getparam_ioctl()
382 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; in i915_getparam_ioctl()
385 value = intel_huc_check_status(&dev_priv->huc); in i915_getparam_ioctl()
397 value = dev_priv->caps.scheduler; in i915_getparam_ioctl()
429 value = intel_engines_has_context_isolation(dev_priv); in i915_getparam_ioctl()
432 value = INTEL_INFO(dev_priv)->sseu.slice_mask; in i915_getparam_ioctl()
437 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0]; in i915_getparam_ioctl()
442 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; in i915_getparam_ioctl()
455 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) in i915_get_bridge_dev() argument
457 int domain = pci_domain_nr(dev_priv->drm.pdev->bus); in i915_get_bridge_dev()
459 dev_priv->bridge_dev = in i915_get_bridge_dev()
461 if (!dev_priv->bridge_dev) { in i915_get_bridge_dev()
470 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) in intel_alloc_mchbar_resource() argument
472 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
477 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
478 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); in intel_alloc_mchbar_resource()
479 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); in intel_alloc_mchbar_resource()
490 dev_priv->mch_res.name = "i915 MCHBAR"; in intel_alloc_mchbar_resource()
491 dev_priv->mch_res.flags = IORESOURCE_MEM; in intel_alloc_mchbar_resource()
492 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, in intel_alloc_mchbar_resource()
493 &dev_priv->mch_res, in intel_alloc_mchbar_resource()
497 dev_priv->bridge_dev); in intel_alloc_mchbar_resource()
500 dev_priv->mch_res.start = 0; in intel_alloc_mchbar_resource()
504 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
505 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, in intel_alloc_mchbar_resource()
506 upper_32_bits(dev_priv->mch_res.start)); in intel_alloc_mchbar_resource()
508 pci_write_config_dword(dev_priv->bridge_dev, reg, in intel_alloc_mchbar_resource()
509 lower_32_bits(dev_priv->mch_res.start)); in intel_alloc_mchbar_resource()
515 intel_setup_mchbar(struct drm_i915_private *dev_priv) in intel_setup_mchbar() argument
517 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
521 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_setup_mchbar()
524 dev_priv->mchbar_need_disable = false; in intel_setup_mchbar()
526 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_setup_mchbar()
527 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); in intel_setup_mchbar()
530 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); in intel_setup_mchbar()
538 if (intel_alloc_mchbar_resource(dev_priv)) in intel_setup_mchbar()
541 dev_priv->mchbar_need_disable = true; in intel_setup_mchbar()
544 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_setup_mchbar()
545 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, in intel_setup_mchbar()
548 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); in intel_setup_mchbar()
549 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); in intel_setup_mchbar()
554 intel_teardown_mchbar(struct drm_i915_private *dev_priv) in intel_teardown_mchbar() argument
556 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
558 if (dev_priv->mchbar_need_disable) { in intel_teardown_mchbar()
559 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_teardown_mchbar()
562 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, in intel_teardown_mchbar()
565 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, in intel_teardown_mchbar()
570 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, in intel_teardown_mchbar()
573 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, in intel_teardown_mchbar()
578 if (dev_priv->mch_res.start) in intel_teardown_mchbar()
579 release_resource(&dev_priv->mch_res); in intel_teardown_mchbar()
585 struct drm_i915_private *dev_priv = cookie; in i915_vga_set_decode() local
587 intel_modeset_vga_set_state(dev_priv, state); in i915_vga_set_decode()
638 struct drm_i915_private *dev_priv = to_i915(dev); in i915_load_modeset_init() local
639 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_load_modeset_init()
645 intel_bios_init(dev_priv); in i915_load_modeset_init()
654 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode); in i915_load_modeset_init()
665 intel_update_rawclk(dev_priv); in i915_load_modeset_init()
667 intel_power_domains_init_hw(dev_priv, false); in i915_load_modeset_init()
669 intel_csr_ucode_init(dev_priv); in i915_load_modeset_init()
671 ret = intel_irq_install(dev_priv); in i915_load_modeset_init()
675 intel_setup_gmbus(dev_priv); in i915_load_modeset_init()
683 ret = i915_gem_init(dev_priv); in i915_load_modeset_init()
687 intel_setup_overlay(dev_priv); in i915_load_modeset_init()
689 if (INTEL_INFO(dev_priv)->num_pipes == 0) in i915_load_modeset_init()
697 intel_hpd_init(dev_priv); in i915_load_modeset_init()
702 if (i915_gem_suspend(dev_priv)) in i915_load_modeset_init()
704 i915_gem_fini(dev_priv); in i915_load_modeset_init()
709 intel_teardown_gmbus(dev_priv); in i915_load_modeset_init()
711 intel_csr_ucode_fini(dev_priv); in i915_load_modeset_init()
712 intel_power_domains_fini(dev_priv); in i915_load_modeset_init()
720 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) in i915_kick_out_firmware_fb() argument
723 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_kick_out_firmware_fb()
724 struct i915_ggtt *ggtt = &dev_priv->ggtt; in i915_kick_out_firmware_fb()
746 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) in i915_kick_out_vgacon() argument
751 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) in i915_kick_out_vgacon() argument
756 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) in i915_kick_out_vgacon() argument
778 static void intel_init_dpio(struct drm_i915_private *dev_priv) in intel_init_dpio() argument
785 if (IS_CHERRYVIEW(dev_priv)) { in intel_init_dpio()
788 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_dpio()
793 static int i915_workqueues_init(struct drm_i915_private *dev_priv) in i915_workqueues_init() argument
809 dev_priv->wq = alloc_ordered_workqueue("i915", 0); in i915_workqueues_init()
810 if (dev_priv->wq == NULL) in i915_workqueues_init()
813 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); in i915_workqueues_init()
814 if (dev_priv->hotplug.dp_wq == NULL) in i915_workqueues_init()
820 destroy_workqueue(dev_priv->wq); in i915_workqueues_init()
836 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) in i915_workqueues_cleanup() argument
838 destroy_workqueue(dev_priv->hotplug.dp_wq); in i915_workqueues_cleanup()
839 destroy_workqueue(dev_priv->wq); in i915_workqueues_cleanup()
852 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) in intel_detect_preproduction_hw() argument
856 pre |= IS_HSW_EARLY_SDV(dev_priv); in intel_detect_preproduction_hw()
857 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); in intel_detect_preproduction_hw()
858 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); in intel_detect_preproduction_hw()
878 static int i915_driver_init_early(struct drm_i915_private *dev_priv, in i915_driver_init_early() argument
890 device_info = mkwrite_device_info(dev_priv); in i915_driver_init_early()
892 device_info->device_id = dev_priv->drm.pdev->device; in i915_driver_init_early()
897 spin_lock_init(&dev_priv->irq_lock); in i915_driver_init_early()
898 spin_lock_init(&dev_priv->gpu_error.lock); in i915_driver_init_early()
899 mutex_init(&dev_priv->backlight_lock); in i915_driver_init_early()
900 spin_lock_init(&dev_priv->uncore.lock); in i915_driver_init_early()
902 mutex_init(&dev_priv->sb_lock); in i915_driver_init_early()
903 mutex_init(&dev_priv->av_mutex); in i915_driver_init_early()
904 mutex_init(&dev_priv->wm.wm_mutex); in i915_driver_init_early()
905 mutex_init(&dev_priv->pps_mutex); in i915_driver_init_early()
907 i915_memcpy_init_early(dev_priv); in i915_driver_init_early()
909 ret = i915_workqueues_init(dev_priv); in i915_driver_init_early()
913 ret = i915_gem_init_early(dev_priv); in i915_driver_init_early()
918 intel_detect_pch(dev_priv); in i915_driver_init_early()
920 intel_wopcm_init_early(&dev_priv->wopcm); in i915_driver_init_early()
921 intel_uc_init_early(dev_priv); in i915_driver_init_early()
922 intel_pm_setup(dev_priv); in i915_driver_init_early()
923 intel_init_dpio(dev_priv); in i915_driver_init_early()
924 intel_power_domains_init(dev_priv); in i915_driver_init_early()
925 intel_irq_init(dev_priv); in i915_driver_init_early()
926 intel_hangcheck_init(dev_priv); in i915_driver_init_early()
927 intel_init_display_hooks(dev_priv); in i915_driver_init_early()
928 intel_init_clock_gating_hooks(dev_priv); in i915_driver_init_early()
929 intel_init_audio_hooks(dev_priv); in i915_driver_init_early()
930 intel_display_crc_init(dev_priv); in i915_driver_init_early()
932 intel_detect_preproduction_hw(dev_priv); in i915_driver_init_early()
937 i915_workqueues_cleanup(dev_priv); in i915_driver_init_early()
939 i915_engines_cleanup(dev_priv); in i915_driver_init_early()
947 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv) in i915_driver_cleanup_early() argument
949 intel_irq_fini(dev_priv); in i915_driver_cleanup_early()
950 intel_uc_cleanup_early(dev_priv); in i915_driver_cleanup_early()
951 i915_gem_cleanup_early(dev_priv); in i915_driver_cleanup_early()
952 i915_workqueues_cleanup(dev_priv); in i915_driver_cleanup_early()
953 i915_engines_cleanup(dev_priv); in i915_driver_cleanup_early()
956 static int i915_mmio_setup(struct drm_i915_private *dev_priv) in i915_mmio_setup() argument
958 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_mmio_setup()
962 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; in i915_mmio_setup()
971 if (INTEL_GEN(dev_priv) < 5) in i915_mmio_setup()
975 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size); in i915_mmio_setup()
976 if (dev_priv->regs == NULL) { in i915_mmio_setup()
983 intel_setup_mchbar(dev_priv); in i915_mmio_setup()
988 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv) in i915_mmio_cleanup() argument
990 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_mmio_cleanup()
992 intel_teardown_mchbar(dev_priv); in i915_mmio_cleanup()
993 pci_iounmap(pdev, dev_priv->regs); in i915_mmio_cleanup()
1005 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) in i915_driver_init_mmio() argument
1012 if (i915_get_bridge_dev(dev_priv)) in i915_driver_init_mmio()
1015 ret = i915_mmio_setup(dev_priv); in i915_driver_init_mmio()
1019 intel_uncore_init(dev_priv); in i915_driver_init_mmio()
1021 intel_device_info_init_mmio(dev_priv); in i915_driver_init_mmio()
1023 intel_uncore_prune(dev_priv); in i915_driver_init_mmio()
1025 intel_uc_init_mmio(dev_priv); in i915_driver_init_mmio()
1027 ret = intel_engines_init_mmio(dev_priv); in i915_driver_init_mmio()
1031 i915_gem_init_mmio(dev_priv); in i915_driver_init_mmio()
1036 intel_uncore_fini(dev_priv); in i915_driver_init_mmio()
1038 pci_dev_put(dev_priv->bridge_dev); in i915_driver_init_mmio()
1047 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) in i915_driver_cleanup_mmio() argument
1049 intel_uncore_fini(dev_priv); in i915_driver_cleanup_mmio()
1050 i915_mmio_cleanup(dev_priv); in i915_driver_cleanup_mmio()
1051 pci_dev_put(dev_priv->bridge_dev); in i915_driver_cleanup_mmio()
1054 static void intel_sanitize_options(struct drm_i915_private *dev_priv) in intel_sanitize_options() argument
1063 intel_sanitize_enable_ppgtt(dev_priv, in intel_sanitize_options()
1067 intel_gvt_sanitize_options(dev_priv); in intel_sanitize_options()
1077 static int i915_driver_init_hw(struct drm_i915_private *dev_priv) in i915_driver_init_hw() argument
1079 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_driver_init_hw()
1085 intel_device_info_runtime_init(mkwrite_device_info(dev_priv)); in i915_driver_init_hw()
1087 intel_sanitize_options(dev_priv); in i915_driver_init_hw()
1089 i915_perf_init(dev_priv); in i915_driver_init_hw()
1091 ret = i915_ggtt_probe_hw(dev_priv); in i915_driver_init_hw()
1099 ret = i915_kick_out_firmware_fb(dev_priv); in i915_driver_init_hw()
1105 ret = i915_kick_out_vgacon(dev_priv); in i915_driver_init_hw()
1111 ret = i915_ggtt_init_hw(dev_priv); in i915_driver_init_hw()
1115 ret = i915_ggtt_enable_hw(dev_priv); in i915_driver_init_hw()
1124 if (IS_GEN2(dev_priv)) { in i915_driver_init_hw()
1141 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { in i915_driver_init_hw()
1151 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, in i915_driver_init_hw()
1154 intel_uncore_sanitize(dev_priv); in i915_driver_init_hw()
1156 i915_gem_load_init_fences(dev_priv); in i915_driver_init_hw()
1177 if (INTEL_GEN(dev_priv) >= 5) { in i915_driver_init_hw()
1182 ret = intel_gvt_init(dev_priv); in i915_driver_init_hw()
1186 intel_opregion_setup(dev_priv); in i915_driver_init_hw()
1193 pm_qos_remove_request(&dev_priv->pm_qos); in i915_driver_init_hw()
1195 i915_ggtt_cleanup_hw(dev_priv); in i915_driver_init_hw()
1197 i915_perf_fini(dev_priv); in i915_driver_init_hw()
1205 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv) in i915_driver_cleanup_hw() argument
1207 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_driver_cleanup_hw()
1209 i915_perf_fini(dev_priv); in i915_driver_cleanup_hw()
1214 pm_qos_remove_request(&dev_priv->pm_qos); in i915_driver_cleanup_hw()
1215 i915_ggtt_cleanup_hw(dev_priv); in i915_driver_cleanup_hw()
1225 static void i915_driver_register(struct drm_i915_private *dev_priv) in i915_driver_register() argument
1227 struct drm_device *dev = &dev_priv->drm; in i915_driver_register()
1229 i915_gem_shrinker_register(dev_priv); in i915_driver_register()
1230 i915_pmu_register(dev_priv); in i915_driver_register()
1236 if (intel_vgpu_active(dev_priv)) in i915_driver_register()
1241 i915_debugfs_register(dev_priv); in i915_driver_register()
1242 i915_setup_sysfs(dev_priv); in i915_driver_register()
1245 i915_perf_register(dev_priv); in i915_driver_register()
1249 if (INTEL_INFO(dev_priv)->num_pipes) { in i915_driver_register()
1251 intel_opregion_register(dev_priv); in i915_driver_register()
1255 if (IS_GEN5(dev_priv)) in i915_driver_register()
1256 intel_gpu_ips_init(dev_priv); in i915_driver_register()
1258 intel_audio_init(dev_priv); in i915_driver_register()
1273 if (INTEL_INFO(dev_priv)->num_pipes) in i915_driver_register()
1281 static void i915_driver_unregister(struct drm_i915_private *dev_priv) in i915_driver_unregister() argument
1283 intel_fbdev_unregister(dev_priv); in i915_driver_unregister()
1284 intel_audio_deinit(dev_priv); in i915_driver_unregister()
1291 drm_kms_helper_poll_fini(&dev_priv->drm); in i915_driver_unregister()
1295 intel_opregion_unregister(dev_priv); in i915_driver_unregister()
1297 i915_perf_unregister(dev_priv); in i915_driver_unregister()
1298 i915_pmu_unregister(dev_priv); in i915_driver_unregister()
1300 i915_teardown_sysfs(dev_priv); in i915_driver_unregister()
1301 drm_dev_unregister(&dev_priv->drm); in i915_driver_unregister()
1303 i915_gem_shrinker_unregister(dev_priv); in i915_driver_unregister()
1306 static void i915_welcome_messages(struct drm_i915_private *dev_priv) in i915_welcome_messages() argument
1311 intel_device_info_dump(&dev_priv->info, &p); in i915_welcome_messages()
1312 intel_device_info_dump_runtime(&dev_priv->info, &p); in i915_welcome_messages()
1336 struct drm_i915_private *dev_priv; in i915_driver_load() local
1344 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); in i915_driver_load()
1345 if (dev_priv) in i915_driver_load()
1346 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev); in i915_driver_load()
1352 dev_priv->drm.pdev = pdev; in i915_driver_load()
1353 dev_priv->drm.dev_private = dev_priv; in i915_driver_load()
1359 pci_set_drvdata(pdev, &dev_priv->drm); in i915_driver_load()
1370 ret = i915_driver_init_early(dev_priv, ent); in i915_driver_load()
1374 intel_runtime_pm_get(dev_priv); in i915_driver_load()
1376 ret = i915_driver_init_mmio(dev_priv); in i915_driver_load()
1380 ret = i915_driver_init_hw(dev_priv); in i915_driver_load()
1389 if (INTEL_INFO(dev_priv)->num_pipes) { in i915_driver_load()
1390 ret = drm_vblank_init(&dev_priv->drm, in i915_driver_load()
1391 INTEL_INFO(dev_priv)->num_pipes); in i915_driver_load()
1396 ret = i915_load_modeset_init(&dev_priv->drm); in i915_driver_load()
1400 i915_driver_register(dev_priv); in i915_driver_load()
1402 intel_runtime_pm_enable(dev_priv); in i915_driver_load()
1404 intel_init_ipc(dev_priv); in i915_driver_load()
1406 intel_runtime_pm_put(dev_priv); in i915_driver_load()
1408 i915_welcome_messages(dev_priv); in i915_driver_load()
1413 i915_driver_cleanup_hw(dev_priv); in i915_driver_load()
1415 i915_driver_cleanup_mmio(dev_priv); in i915_driver_load()
1417 intel_runtime_pm_put(dev_priv); in i915_driver_load()
1418 i915_driver_cleanup_early(dev_priv); in i915_driver_load()
1422 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret); in i915_driver_load()
1423 drm_dev_fini(&dev_priv->drm); in i915_driver_load()
1425 kfree(dev_priv); in i915_driver_load()
1432 struct drm_i915_private *dev_priv = to_i915(dev); in i915_driver_unload() local
1433 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_driver_unload()
1435 i915_driver_unregister(dev_priv); in i915_driver_unload()
1437 if (i915_gem_suspend(dev_priv)) in i915_driver_unload()
1440 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); in i915_driver_unload()
1444 intel_gvt_cleanup(dev_priv); in i915_driver_unload()
1448 intel_bios_cleanup(dev_priv); in i915_driver_unload()
1453 intel_csr_ucode_fini(dev_priv); in i915_driver_unload()
1456 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); in i915_driver_unload()
1457 i915_reset_error_state(dev_priv); in i915_driver_unload()
1459 i915_gem_fini(dev_priv); in i915_driver_unload()
1460 intel_fbc_cleanup_cfb(dev_priv); in i915_driver_unload()
1462 intel_power_domains_fini(dev_priv); in i915_driver_unload()
1464 i915_driver_cleanup_hw(dev_priv); in i915_driver_unload()
1465 i915_driver_cleanup_mmio(dev_priv); in i915_driver_unload()
1467 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in i915_driver_unload()
1472 struct drm_i915_private *dev_priv = to_i915(dev); in i915_driver_release() local
1474 i915_driver_cleanup_early(dev_priv); in i915_driver_release()
1475 drm_dev_fini(&dev_priv->drm); in i915_driver_release()
1477 kfree(dev_priv); in i915_driver_release()
1522 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) in intel_suspend_encoders() argument
1524 struct drm_device *dev = &dev_priv->drm; in intel_suspend_encoders()
1534 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1536 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1538 static bool suspend_to_idle(struct drm_i915_private *dev_priv) in suspend_to_idle() argument
1568 struct drm_i915_private *dev_priv = to_i915(dev); in i915_drm_suspend() local
1569 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_drm_suspend()
1572 disable_rpm_wakeref_asserts(dev_priv); in i915_drm_suspend()
1576 intel_display_set_init_power(dev_priv, true); in i915_drm_suspend()
1584 intel_dp_mst_suspend(dev_priv); in i915_drm_suspend()
1586 intel_runtime_pm_disable_interrupts(dev_priv); in i915_drm_suspend()
1587 intel_hpd_cancel_work(dev_priv); in i915_drm_suspend()
1589 intel_suspend_encoders(dev_priv); in i915_drm_suspend()
1591 intel_suspend_hw(dev_priv); in i915_drm_suspend()
1593 i915_gem_suspend_gtt_mappings(dev_priv); in i915_drm_suspend()
1595 i915_save_state(dev_priv); in i915_drm_suspend()
1597 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; in i915_drm_suspend()
1598 intel_opregion_notify_adapter(dev_priv, opregion_target_state); in i915_drm_suspend()
1600 intel_opregion_unregister(dev_priv); in i915_drm_suspend()
1604 dev_priv->suspend_count++; in i915_drm_suspend()
1606 intel_csr_ucode_suspend(dev_priv); in i915_drm_suspend()
1608 enable_rpm_wakeref_asserts(dev_priv); in i915_drm_suspend()
1615 struct drm_i915_private *dev_priv = to_i915(dev); in i915_drm_suspend_late() local
1616 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_drm_suspend_late()
1619 disable_rpm_wakeref_asserts(dev_priv); in i915_drm_suspend_late()
1621 i915_gem_suspend_late(dev_priv); in i915_drm_suspend_late()
1623 intel_display_set_init_power(dev_priv, false); in i915_drm_suspend_late()
1624 intel_uncore_suspend(dev_priv); in i915_drm_suspend_late()
1633 if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) || in i915_drm_suspend_late()
1634 dev_priv->csr.dmc_payload == NULL) { in i915_drm_suspend_late()
1635 intel_power_domains_suspend(dev_priv); in i915_drm_suspend_late()
1636 dev_priv->power_domains_suspended = true; in i915_drm_suspend_late()
1640 if (IS_GEN9_LP(dev_priv)) in i915_drm_suspend_late()
1641 bxt_enable_dc9(dev_priv); in i915_drm_suspend_late()
1642 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in i915_drm_suspend_late()
1643 hsw_enable_pc8(dev_priv); in i915_drm_suspend_late()
1644 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i915_drm_suspend_late()
1645 ret = vlv_suspend_complete(dev_priv); in i915_drm_suspend_late()
1649 if (dev_priv->power_domains_suspended) { in i915_drm_suspend_late()
1650 intel_power_domains_init_hw(dev_priv, true); in i915_drm_suspend_late()
1651 dev_priv->power_domains_suspended = false; in i915_drm_suspend_late()
1670 if (!(hibernation && INTEL_GEN(dev_priv) < 6)) in i915_drm_suspend_late()
1674 enable_rpm_wakeref_asserts(dev_priv); in i915_drm_suspend_late()
1705 struct drm_i915_private *dev_priv = to_i915(dev); in i915_drm_resume() local
1708 disable_rpm_wakeref_asserts(dev_priv); in i915_drm_resume()
1709 intel_sanitize_gt_powersave(dev_priv); in i915_drm_resume()
1711 i915_gem_sanitize(dev_priv); in i915_drm_resume()
1713 ret = i915_ggtt_enable_hw(dev_priv); in i915_drm_resume()
1717 intel_csr_ucode_resume(dev_priv); in i915_drm_resume()
1719 i915_restore_state(dev_priv); in i915_drm_resume()
1720 intel_pps_unlock_regs_wa(dev_priv); in i915_drm_resume()
1721 intel_opregion_setup(dev_priv); in i915_drm_resume()
1723 intel_init_pch_refclk(dev_priv); in i915_drm_resume()
1735 intel_runtime_pm_enable_interrupts(dev_priv); in i915_drm_resume()
1739 i915_gem_resume(dev_priv); in i915_drm_resume()
1742 intel_init_clock_gating(dev_priv); in i915_drm_resume()
1744 spin_lock_irq(&dev_priv->irq_lock); in i915_drm_resume()
1745 if (dev_priv->display.hpd_irq_setup) in i915_drm_resume()
1746 dev_priv->display.hpd_irq_setup(dev_priv); in i915_drm_resume()
1747 spin_unlock_irq(&dev_priv->irq_lock); in i915_drm_resume()
1749 intel_dp_mst_resume(dev_priv); in i915_drm_resume()
1761 intel_hpd_init(dev_priv); in i915_drm_resume()
1763 intel_opregion_register(dev_priv); in i915_drm_resume()
1767 intel_opregion_notify_adapter(dev_priv, PCI_D0); in i915_drm_resume()
1769 enable_rpm_wakeref_asserts(dev_priv); in i915_drm_resume()
1776 struct drm_i915_private *dev_priv = to_i915(dev); in i915_drm_resume_early() local
1777 struct pci_dev *pdev = dev_priv->drm.pdev; in i915_drm_resume_early()
1826 disable_rpm_wakeref_asserts(dev_priv); in i915_drm_resume_early()
1828 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i915_drm_resume_early()
1829 ret = vlv_resume_prepare(dev_priv, false); in i915_drm_resume_early()
1834 intel_uncore_resume_early(dev_priv); in i915_drm_resume_early()
1836 if (IS_GEN9_LP(dev_priv)) { in i915_drm_resume_early()
1837 gen9_sanitize_dc_state(dev_priv); in i915_drm_resume_early()
1838 bxt_disable_dc9(dev_priv); in i915_drm_resume_early()
1839 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in i915_drm_resume_early()
1840 hsw_disable_pc8(dev_priv); in i915_drm_resume_early()
1843 intel_uncore_sanitize(dev_priv); in i915_drm_resume_early()
1845 if (dev_priv->power_domains_suspended) in i915_drm_resume_early()
1846 intel_power_domains_init_hw(dev_priv, true); in i915_drm_resume_early()
1848 intel_display_set_init_power(dev_priv, true); in i915_drm_resume_early()
1850 intel_engines_sanitize(dev_priv); in i915_drm_resume_early()
1852 enable_rpm_wakeref_asserts(dev_priv); in i915_drm_resume_early()
1855 dev_priv->power_domains_suspended = false; in i915_drm_resume_early()
2007 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv, in intel_gt_reset_engine() argument
2010 return intel_gpu_reset(dev_priv, intel_engine_flag(engine)); in intel_gt_reset_engine()
2246 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) in vlv_save_gunit_s0ix_state() argument
2248 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; in vlv_save_gunit_s0ix_state()
2327 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) in vlv_restore_gunit_s0ix_state() argument
2329 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; in vlv_restore_gunit_s0ix_state()
2414 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv, in vlv_wait_for_pw_status() argument
2428 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) in vlv_force_gfx_clock() argument
2442 err = intel_wait_for_register(dev_priv, in vlv_force_gfx_clock()
2454 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) in vlv_allow_gt_wake() argument
2470 err = vlv_wait_for_pw_status(dev_priv, mask, val); in vlv_allow_gt_wake()
2477 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, in vlv_wait_for_gt_wells() argument
2493 if (vlv_wait_for_pw_status(dev_priv, mask, val)) in vlv_wait_for_gt_wells()
2498 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) in vlv_check_no_gt_access() argument
2507 static int vlv_suspend_complete(struct drm_i915_private *dev_priv) in vlv_suspend_complete() argument
2516 vlv_wait_for_gt_wells(dev_priv, false); in vlv_suspend_complete()
2521 vlv_check_no_gt_access(dev_priv); in vlv_suspend_complete()
2523 err = vlv_force_gfx_clock(dev_priv, true); in vlv_suspend_complete()
2527 err = vlv_allow_gt_wake(dev_priv, false); in vlv_suspend_complete()
2531 if (!IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
2532 vlv_save_gunit_s0ix_state(dev_priv); in vlv_suspend_complete()
2534 err = vlv_force_gfx_clock(dev_priv, false); in vlv_suspend_complete()
2542 vlv_allow_gt_wake(dev_priv, true); in vlv_suspend_complete()
2544 vlv_force_gfx_clock(dev_priv, false); in vlv_suspend_complete()
2549 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, in vlv_resume_prepare() argument
2560 ret = vlv_force_gfx_clock(dev_priv, true); in vlv_resume_prepare()
2562 if (!IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
2563 vlv_restore_gunit_s0ix_state(dev_priv); in vlv_resume_prepare()
2565 err = vlv_allow_gt_wake(dev_priv, true); in vlv_resume_prepare()
2569 err = vlv_force_gfx_clock(dev_priv, false); in vlv_resume_prepare()
2573 vlv_check_no_gt_access(dev_priv); in vlv_resume_prepare()
2576 intel_init_clock_gating(dev_priv); in vlv_resume_prepare()
2585 struct drm_i915_private *dev_priv = to_i915(dev); in intel_runtime_suspend() local
2588 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv)))) in intel_runtime_suspend()
2591 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) in intel_runtime_suspend()
2596 disable_rpm_wakeref_asserts(dev_priv); in intel_runtime_suspend()
2602 i915_gem_runtime_suspend(dev_priv); in intel_runtime_suspend()
2604 intel_uc_suspend(dev_priv); in intel_runtime_suspend()
2606 intel_runtime_pm_disable_interrupts(dev_priv); in intel_runtime_suspend()
2608 intel_uncore_suspend(dev_priv); in intel_runtime_suspend()
2611 if (IS_GEN9_LP(dev_priv)) { in intel_runtime_suspend()
2612 bxt_display_core_uninit(dev_priv); in intel_runtime_suspend()
2613 bxt_enable_dc9(dev_priv); in intel_runtime_suspend()
2614 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in intel_runtime_suspend()
2615 hsw_enable_pc8(dev_priv); in intel_runtime_suspend()
2616 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_runtime_suspend()
2617 ret = vlv_suspend_complete(dev_priv); in intel_runtime_suspend()
2622 intel_uncore_runtime_resume(dev_priv); in intel_runtime_suspend()
2624 intel_runtime_pm_enable_interrupts(dev_priv); in intel_runtime_suspend()
2626 intel_uc_resume(dev_priv); in intel_runtime_suspend()
2628 i915_gem_init_swizzling(dev_priv); in intel_runtime_suspend()
2629 i915_gem_restore_fences(dev_priv); in intel_runtime_suspend()
2631 enable_rpm_wakeref_asserts(dev_priv); in intel_runtime_suspend()
2636 enable_rpm_wakeref_asserts(dev_priv); in intel_runtime_suspend()
2637 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count)); in intel_runtime_suspend()
2639 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) in intel_runtime_suspend()
2642 dev_priv->runtime_pm.suspended = true; in intel_runtime_suspend()
2648 if (IS_BROADWELL(dev_priv)) { in intel_runtime_suspend()
2655 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); in intel_runtime_suspend()
2664 intel_opregion_notify_adapter(dev_priv, PCI_D1); in intel_runtime_suspend()
2667 assert_forcewakes_inactive(dev_priv); in intel_runtime_suspend()
2669 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_runtime_suspend()
2670 intel_hpd_poll_init(dev_priv); in intel_runtime_suspend()
2680 struct drm_i915_private *dev_priv = to_i915(dev); in intel_runtime_resume() local
2683 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) in intel_runtime_resume()
2688 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count)); in intel_runtime_resume()
2689 disable_rpm_wakeref_asserts(dev_priv); in intel_runtime_resume()
2691 intel_opregion_notify_adapter(dev_priv, PCI_D0); in intel_runtime_resume()
2692 dev_priv->runtime_pm.suspended = false; in intel_runtime_resume()
2693 if (intel_uncore_unclaimed_mmio(dev_priv)) in intel_runtime_resume()
2696 if (IS_GEN9_LP(dev_priv)) { in intel_runtime_resume()
2697 bxt_disable_dc9(dev_priv); in intel_runtime_resume()
2698 bxt_display_core_init(dev_priv, true); in intel_runtime_resume()
2699 if (dev_priv->csr.dmc_payload && in intel_runtime_resume()
2700 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) in intel_runtime_resume()
2701 gen9_enable_dc5(dev_priv); in intel_runtime_resume()
2702 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in intel_runtime_resume()
2703 hsw_disable_pc8(dev_priv); in intel_runtime_resume()
2704 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_runtime_resume()
2705 ret = vlv_resume_prepare(dev_priv, true); in intel_runtime_resume()
2708 intel_uncore_runtime_resume(dev_priv); in intel_runtime_resume()
2710 intel_runtime_pm_enable_interrupts(dev_priv); in intel_runtime_resume()
2712 intel_uc_resume(dev_priv); in intel_runtime_resume()
2718 i915_gem_init_swizzling(dev_priv); in intel_runtime_resume()
2719 i915_gem_restore_fences(dev_priv); in intel_runtime_resume()
2726 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_runtime_resume()
2727 intel_hpd_init(dev_priv); in intel_runtime_resume()
2729 intel_enable_ipc(dev_priv); in intel_runtime_resume()
2731 enable_rpm_wakeref_asserts(dev_priv); in intel_runtime_resume()