Lines Matching refs:seq_printf
46 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); in i915_capabilities()
47 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); in i915_capabilities()
48 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); in i915_capabilities()
145 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", in describe_obj()
159 seq_printf(m, " (name: %d)", obj->base.name); in describe_obj()
164 seq_printf(m, " (pinned x %d)", pin_count); in describe_obj()
166 seq_printf(m, " (global)"); in describe_obj()
171 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", in describe_obj()
182 seq_printf(m, ", partial [%08llx+%x]", in describe_obj()
188 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", in describe_obj()
205 seq_printf(m, " , fence: %d%s", in describe_obj()
211 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); in describe_obj()
215 seq_printf(m, " (%s)", engine->name); in describe_obj()
219 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); in describe_obj()
290 seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", in i915_gem_stolen_list_info()
346 …seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, …
437 seq_printf(m, "%u objects, %llu bytes\n", in i915_gem_object_info()
467 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); in i915_gem_object_info()
497 seq_printf(m, "%u bound objects, %llu bytes\n", in i915_gem_object_info()
499 seq_printf(m, "%u purgeable objects, %llu bytes\n", in i915_gem_object_info()
501 seq_printf(m, "%u mapped objects, %llu bytes\n", in i915_gem_object_info()
503 seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n", in i915_gem_object_info()
507 seq_printf(m, "%u display objects (globally pinned), %llu bytes\n", in i915_gem_object_info()
510 seq_printf(m, "%llu [%pa] gtt total\n", in i915_gem_object_info()
512 seq_printf(m, "Supported page sizes: %s\n", in i915_gem_object_info()
600 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", in i915_gem_gtt_info()
630 seq_printf(m, "%s cache[%d]: %d objects\n", in i915_gem_batch_pool_info()
645 seq_printf(m, "total: %d\n", total); in i915_gem_batch_pool_info()
663 seq_printf(m, "Pipe %c power disabled\n", in gen8_display_interrupt_info()
667 seq_printf(m, "Pipe %c IMR:\t%08x\n", in gen8_display_interrupt_info()
670 seq_printf(m, "Pipe %c IIR:\t%08x\n", in gen8_display_interrupt_info()
673 seq_printf(m, "Pipe %c IER:\t%08x\n", in gen8_display_interrupt_info()
680 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", in gen8_display_interrupt_info()
682 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", in gen8_display_interrupt_info()
684 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", in gen8_display_interrupt_info()
687 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", in gen8_display_interrupt_info()
689 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", in gen8_display_interrupt_info()
691 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", in gen8_display_interrupt_info()
694 seq_printf(m, "PCU interrupt mask:\t%08x\n", in gen8_display_interrupt_info()
696 seq_printf(m, "PCU interrupt identity:\t%08x\n", in gen8_display_interrupt_info()
698 seq_printf(m, "PCU interrupt enable:\t%08x\n", in gen8_display_interrupt_info()
712 seq_printf(m, "Master Interrupt Control:\t%08x\n", in i915_interrupt_info()
715 seq_printf(m, "Display IER:\t%08x\n", in i915_interrupt_info()
717 seq_printf(m, "Display IIR:\t%08x\n", in i915_interrupt_info()
719 seq_printf(m, "Display IIR_RW:\t%08x\n", in i915_interrupt_info()
721 seq_printf(m, "Display IMR:\t%08x\n", in i915_interrupt_info()
729 seq_printf(m, "Pipe %c power disabled\n", in i915_interrupt_info()
734 seq_printf(m, "Pipe %c stat:\t%08x\n", in i915_interrupt_info()
742 seq_printf(m, "Port hotplug:\t%08x\n", in i915_interrupt_info()
744 seq_printf(m, "DPFLIPSTAT:\t%08x\n", in i915_interrupt_info()
746 seq_printf(m, "DPINVGTT:\t%08x\n", in i915_interrupt_info()
751 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", in i915_interrupt_info()
753 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", in i915_interrupt_info()
755 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", in i915_interrupt_info()
759 seq_printf(m, "PCU interrupt mask:\t%08x\n", in i915_interrupt_info()
761 seq_printf(m, "PCU interrupt identity:\t%08x\n", in i915_interrupt_info()
763 seq_printf(m, "PCU interrupt enable:\t%08x\n", in i915_interrupt_info()
766 seq_printf(m, "Master Interrupt Control: %08x\n", in i915_interrupt_info()
769 seq_printf(m, "Render/Copy Intr Enable: %08x\n", in i915_interrupt_info()
771 seq_printf(m, "VCS/VECS Intr Enable: %08x\n", in i915_interrupt_info()
773 seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", in i915_interrupt_info()
775 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", in i915_interrupt_info()
777 seq_printf(m, "Crypto Intr Enable:\t %08x\n", in i915_interrupt_info()
779 seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", in i915_interrupt_info()
782 seq_printf(m, "Display Interrupt Control:\t%08x\n", in i915_interrupt_info()
787 seq_printf(m, "Master Interrupt Control:\t%08x\n", in i915_interrupt_info()
791 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", in i915_interrupt_info()
793 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", in i915_interrupt_info()
795 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", in i915_interrupt_info()
801 seq_printf(m, "Display IER:\t%08x\n", in i915_interrupt_info()
803 seq_printf(m, "Display IIR:\t%08x\n", in i915_interrupt_info()
805 seq_printf(m, "Display IIR_RW:\t%08x\n", in i915_interrupt_info()
807 seq_printf(m, "Display IMR:\t%08x\n", in i915_interrupt_info()
815 seq_printf(m, "Pipe %c power disabled\n", in i915_interrupt_info()
820 seq_printf(m, "Pipe %c stat:\t%08x\n", in i915_interrupt_info()
826 seq_printf(m, "Master IER:\t%08x\n", in i915_interrupt_info()
829 seq_printf(m, "Render IER:\t%08x\n", in i915_interrupt_info()
831 seq_printf(m, "Render IIR:\t%08x\n", in i915_interrupt_info()
833 seq_printf(m, "Render IMR:\t%08x\n", in i915_interrupt_info()
836 seq_printf(m, "PM IER:\t\t%08x\n", in i915_interrupt_info()
838 seq_printf(m, "PM IIR:\t\t%08x\n", in i915_interrupt_info()
840 seq_printf(m, "PM IMR:\t\t%08x\n", in i915_interrupt_info()
843 seq_printf(m, "Port hotplug:\t%08x\n", in i915_interrupt_info()
845 seq_printf(m, "DPFLIPSTAT:\t%08x\n", in i915_interrupt_info()
847 seq_printf(m, "DPINVGTT:\t%08x\n", in i915_interrupt_info()
851 seq_printf(m, "Interrupt enable: %08x\n", in i915_interrupt_info()
853 seq_printf(m, "Interrupt identity: %08x\n", in i915_interrupt_info()
855 seq_printf(m, "Interrupt mask: %08x\n", in i915_interrupt_info()
858 seq_printf(m, "Pipe %c stat: %08x\n", in i915_interrupt_info()
862 seq_printf(m, "North Display Interrupt enable: %08x\n", in i915_interrupt_info()
864 seq_printf(m, "North Display Interrupt identity: %08x\n", in i915_interrupt_info()
866 seq_printf(m, "North Display Interrupt mask: %08x\n", in i915_interrupt_info()
868 seq_printf(m, "South Display Interrupt enable: %08x\n", in i915_interrupt_info()
870 seq_printf(m, "South Display Interrupt identity: %08x\n", in i915_interrupt_info()
872 seq_printf(m, "South Display Interrupt mask: %08x\n", in i915_interrupt_info()
874 seq_printf(m, "Graphics Interrupt enable: %08x\n", in i915_interrupt_info()
876 seq_printf(m, "Graphics Interrupt identity: %08x\n", in i915_interrupt_info()
878 seq_printf(m, "Graphics Interrupt mask: %08x\n", in i915_interrupt_info()
883 seq_printf(m, "RCS Intr Mask:\t %08x\n", in i915_interrupt_info()
885 seq_printf(m, "BCS Intr Mask:\t %08x\n", in i915_interrupt_info()
887 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", in i915_interrupt_info()
889 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", in i915_interrupt_info()
891 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", in i915_interrupt_info()
893 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", in i915_interrupt_info()
895 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", in i915_interrupt_info()
897 seq_printf(m, "Crypto Intr Mask:\t %08x\n", in i915_interrupt_info()
899 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", in i915_interrupt_info()
904 seq_printf(m, in i915_interrupt_info()
925 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); in i915_gem_fence_regs_info()
929 seq_printf(m, "Fence %d, pin count = %d, object = ", in i915_gem_fence_regs_info()
1071 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); in i915_frequency_info()
1072 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); in i915_frequency_info()
1073 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> in i915_frequency_info()
1075 seq_printf(m, "Current P-state: %d\n", in i915_frequency_info()
1083 seq_printf(m, "Video Turbo Mode: %s\n", in i915_frequency_info()
1085 seq_printf(m, "HW control enabled: %s\n", in i915_frequency_info()
1087 seq_printf(m, "SW control enabled: %s\n", in i915_frequency_info()
1092 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); in i915_frequency_info()
1093 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); in i915_frequency_info()
1095 seq_printf(m, "actual GPU freq: %d MHz\n", in i915_frequency_info()
1098 seq_printf(m, "current GPU freq: %d MHz\n", in i915_frequency_info()
1101 seq_printf(m, "max GPU freq: %d MHz\n", in i915_frequency_info()
1104 seq_printf(m, "min GPU freq: %d MHz\n", in i915_frequency_info()
1107 seq_printf(m, "idle GPU freq: %d MHz\n", in i915_frequency_info()
1110 seq_printf(m, in i915_frequency_info()
1187 seq_printf(m, "Video Turbo Mode: %s\n", in i915_frequency_info()
1189 seq_printf(m, "HW control enabled: %s\n", in i915_frequency_info()
1191 seq_printf(m, "SW control enabled: %s\n", in i915_frequency_info()
1195 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", in i915_frequency_info()
1198 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", in i915_frequency_info()
1200 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", in i915_frequency_info()
1202 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); in i915_frequency_info()
1203 seq_printf(m, "Render p-state ratio: %d\n", in i915_frequency_info()
1205 seq_printf(m, "Render p-state VID: %d\n", in i915_frequency_info()
1207 seq_printf(m, "Render p-state limit: %d\n", in i915_frequency_info()
1209 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); in i915_frequency_info()
1210 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); in i915_frequency_info()
1211 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); in i915_frequency_info()
1212 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); in i915_frequency_info()
1213 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); in i915_frequency_info()
1214 seq_printf(m, "CAGF: %dMHz\n", cagf); in i915_frequency_info()
1215 seq_printf(m, "RP CUR UP EI: %d (%dus)\n", in i915_frequency_info()
1217 seq_printf(m, "RP CUR UP: %d (%dus)\n", in i915_frequency_info()
1219 seq_printf(m, "RP PREV UP: %d (%dus)\n", in i915_frequency_info()
1221 seq_printf(m, "Up threshold: %d%%\n", in i915_frequency_info()
1224 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", in i915_frequency_info()
1226 seq_printf(m, "RP CUR DOWN: %d (%dus)\n", in i915_frequency_info()
1228 seq_printf(m, "RP PREV DOWN: %d (%dus)\n", in i915_frequency_info()
1230 seq_printf(m, "Down threshold: %d%%\n", in i915_frequency_info()
1237 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", in i915_frequency_info()
1243 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", in i915_frequency_info()
1250 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", in i915_frequency_info()
1252 seq_printf(m, "Max overclocked frequency: %dMHz\n", in i915_frequency_info()
1255 seq_printf(m, "Current freq: %d MHz\n", in i915_frequency_info()
1257 seq_printf(m, "Actual freq: %d MHz\n", cagf); in i915_frequency_info()
1258 seq_printf(m, "Idle freq: %d MHz\n", in i915_frequency_info()
1260 seq_printf(m, "Min freq: %d MHz\n", in i915_frequency_info()
1262 seq_printf(m, "Boost freq: %d MHz\n", in i915_frequency_info()
1264 seq_printf(m, "Max freq: %d MHz\n", in i915_frequency_info()
1266 seq_printf(m, in i915_frequency_info()
1273 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); in i915_frequency_info()
1274 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); in i915_frequency_info()
1275 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); in i915_frequency_info()
1288 seq_printf(m, "\t\tINSTDONE: 0x%08x\n", in i915_instdone_info()
1294 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", in i915_instdone_info()
1301 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", in i915_instdone_info()
1305 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", in i915_instdone_info()
1346 seq_printf(m, "Hangcheck active, timer fires in %dms\n", in i915_hangcheck_info()
1354 seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); in i915_hangcheck_info()
1360 seq_printf(m, "%s:\n", engine->name); in i915_hangcheck_info()
1361 seq_printf(m, "\tseqno = %x [current %x, last %x]\n", in i915_hangcheck_info()
1364 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s, wedged? %s\n", in i915_hangcheck_info()
1375 seq_printf(m, "\t%s [%d] waiting for %x\n", in i915_hangcheck_info()
1380 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", in i915_hangcheck_info()
1383 seq_printf(m, "\taction = %s(%d) %d ms ago\n", in i915_hangcheck_info()
1411 seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); in i915_reset_info()
1414 seq_printf(m, "%s = %u\n", engine->name, in i915_reset_info()
1431 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); in ironlake_drpc_info()
1432 seq_printf(m, "Boost freq: %d\n", in ironlake_drpc_info()
1435 seq_printf(m, "HW control enabled: %s\n", in ironlake_drpc_info()
1437 seq_printf(m, "SW control enabled: %s\n", in ironlake_drpc_info()
1439 seq_printf(m, "Gated voltage change: %s\n", in ironlake_drpc_info()
1441 seq_printf(m, "Starting frequency: P%d\n", in ironlake_drpc_info()
1443 seq_printf(m, "Max P-state: P%d\n", in ironlake_drpc_info()
1445 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); in ironlake_drpc_info()
1446 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); in ironlake_drpc_info()
1447 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); in ironlake_drpc_info()
1448 seq_printf(m, "Render standby enabled: %s\n", in ironlake_drpc_info()
1484 seq_printf(m, "user.bypass_count = %u\n", in i915_forcewake_domains()
1488 seq_printf(m, "%s.wake_count = %u\n", in i915_forcewake_domains()
1501 seq_printf(m, "%s %u (%llu us)\n", in print_rc6_res()
1514 seq_printf(m, "RC6 Enabled: %s\n", in vlv_drpc_info()
1517 seq_printf(m, "Render Power Well: %s\n", in vlv_drpc_info()
1519 seq_printf(m, "Media Power Well: %s\n", in vlv_drpc_info()
1550 seq_printf(m, "RC1e Enabled: %s\n", in gen6_drpc_info()
1552 seq_printf(m, "RC6 Enabled: %s\n", in gen6_drpc_info()
1555 seq_printf(m, "Render Well Gating Enabled: %s\n", in gen6_drpc_info()
1557 seq_printf(m, "Media Well Gating Enabled: %s\n", in gen6_drpc_info()
1560 seq_printf(m, "Deep RC6 Enabled: %s\n", in gen6_drpc_info()
1562 seq_printf(m, "Deepest RC6 Enabled: %s\n", in gen6_drpc_info()
1586 seq_printf(m, "Core Power Down: %s\n", in gen6_drpc_info()
1589 seq_printf(m, "Render Power Well: %s\n", in gen6_drpc_info()
1592 seq_printf(m, "Media Power Well: %s\n", in gen6_drpc_info()
1605 seq_printf(m, "RC6 voltage: %dmV\n", in gen6_drpc_info()
1607 seq_printf(m, "RC6+ voltage: %dmV\n", in gen6_drpc_info()
1609 seq_printf(m, "RC6++ voltage: %dmV\n", in gen6_drpc_info()
1639 seq_printf(m, "FB tracking busy bits: 0x%08x\n", in i915_frontbuffer_tracking()
1642 seq_printf(m, "FB tracking flip bits: 0x%08x\n", in i915_frontbuffer_tracking()
1662 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); in i915_fbc_status()
1679 seq_printf(m, "Compressing: %s\n", yesno(mask)); in i915_fbc_status()
1734 seq_printf(m, "Enabled by kernel parameter: %s\n", in i915_ips_status()
1776 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); in i915_sr_status()
1800 seq_printf(m, "GMCH temp: %ld\n", temp); in i915_emon_status()
1801 seq_printf(m, "Chipset power: %ld\n", chipset); in i915_emon_status()
1802 seq_printf(m, "GFX power: %ld\n", gfx); in i915_emon_status()
1803 seq_printf(m, "Total power: %ld\n", chipset + gfx); in i915_emon_status()
1840 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", in i915_ring_freq_table()
1902 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", in i915_gem_framebuffer_info()
1920 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", in i915_gem_framebuffer_info()
1938 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)", in describe_ctx_ring()
1956 seq_printf(m, "HW context %u ", ctx->hw_id); in i915_context_status()
1962 seq_printf(m, "(%s [%d]) ", in i915_context_status()
1979 seq_printf(m, "%s: ", engine->name); in i915_context_status()
2025 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", in i915_swizzle_info()
2027 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", in i915_swizzle_info()
2031 seq_printf(m, "DDC = 0x%08x\n", in i915_swizzle_info()
2033 seq_printf(m, "DDC2 = 0x%08x\n", in i915_swizzle_info()
2035 seq_printf(m, "C0DRB3 = 0x%04x\n", in i915_swizzle_info()
2037 seq_printf(m, "C1DRB3 = 0x%04x\n", in i915_swizzle_info()
2040 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", in i915_swizzle_info()
2042 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", in i915_swizzle_info()
2044 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", in i915_swizzle_info()
2046 seq_printf(m, "TILECTL = 0x%08x\n", in i915_swizzle_info()
2049 seq_printf(m, "GAMTARBMODE = 0x%08x\n", in i915_swizzle_info()
2052 seq_printf(m, "ARB_MODE = 0x%08x\n", in i915_swizzle_info()
2054 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", in i915_swizzle_info()
2073 seq_printf(m, " no ppgtt for context %d\n", in per_file_ctx()
2081 seq_printf(m, " context %d:\n", ctx->user_handle); in per_file_ctx()
2099 seq_printf(m, "%s\n", engine->name); in gen8_ppgtt_info()
2104 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); in gen8_ppgtt_info()
2116 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); in gen6_ppgtt_info()
2119 seq_printf(m, "%s\n", engine->name); in gen6_ppgtt_info()
2121 seq_printf(m, "GFX_MODE: 0x%08x\n", in gen6_ppgtt_info()
2123 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", in gen6_ppgtt_info()
2125 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", in gen6_ppgtt_info()
2127 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", in gen6_ppgtt_info()
2134 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); in gen6_ppgtt_info()
2139 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); in gen6_ppgtt_info()
2170 seq_printf(m, "\nproc: %s\n", task->comm); in i915_ppgtt_info()
2217 seq_printf(m, "RPS enabled? %d\n", rps->enabled); in i915_rps_boost_info()
2218 seq_printf(m, "GPU busy? %s [%d requests]\n", in i915_rps_boost_info()
2220 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); in i915_rps_boost_info()
2221 seq_printf(m, "Boosts outstanding? %d\n", in i915_rps_boost_info()
2223 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); in i915_rps_boost_info()
2224 seq_printf(m, "Frequency requested %d\n", in i915_rps_boost_info()
2226 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", in i915_rps_boost_info()
2231 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", in i915_rps_boost_info()
2243 seq_printf(m, "%s [%d]: %d boosts\n", in i915_rps_boost_info()
2249 seq_printf(m, "Kernel (anonymous) boosts: %d\n", in i915_rps_boost_info()
2266 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", in i915_rps_boost_info()
2268 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", in i915_rps_boost_info()
2271 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", in i915_rps_boost_info()
2286 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); in i915_llc()
2287 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", in i915_llc()
2305 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); in i915_huc_load_status_info()
2327 seq_printf(m, "\nGuC status 0x%08x:\n", tmp); in i915_guc_load_status_info()
2328 seq_printf(m, "\tBootrom status = 0x%x\n", in i915_guc_load_status_info()
2330 seq_printf(m, "\tuKernel status = 0x%x\n", in i915_guc_load_status_info()
2332 seq_printf(m, "\tMIA Core status = 0x%x\n", in i915_guc_load_status_info()
2336 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); in i915_guc_load_status_info()
2373 seq_printf(m, "\tRelay full count: %u\n", in i915_guc_log_info()
2377 seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n", in i915_guc_log_info()
2392 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", in i915_guc_client_info()
2394 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n", in i915_guc_client_info()
2400 seq_printf(m, "\tSubmissions: %llu %s\n", in i915_guc_client_info()
2403 seq_printf(m, "\tTotal: %llu\n", tot); in i915_guc_client_info()
2421 seq_printf(m, "\nDoorbell map:\n"); in i915_guc_info()
2422 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); in i915_guc_info()
2423 seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline); in i915_guc_info()
2425 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); in i915_guc_info()
2428 seq_printf(m, "\nGuC preempt client @ %p:\n", in i915_guc_info()
2456 seq_printf(m, "GuC stage descriptor %u:\n", index); in i915_guc_stage_pool()
2457 seq_printf(m, "\tIndex: %u\n", desc->stage_id); in i915_guc_stage_pool()
2458 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); in i915_guc_stage_pool()
2459 seq_printf(m, "\tPriority: %d\n", desc->priority); in i915_guc_stage_pool()
2460 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); in i915_guc_stage_pool()
2461 seq_printf(m, "\tEngines used: 0x%x\n", in i915_guc_stage_pool()
2463 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", in i915_guc_stage_pool()
2467 seq_printf(m, "\tProcess descriptor: 0x%x\n", in i915_guc_stage_pool()
2469 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", in i915_guc_stage_pool()
2478 seq_printf(m, "\t%s LRC:\n", engine->name); in i915_guc_stage_pool()
2479 seq_printf(m, "\t\tContext desc: 0x%x\n", in i915_guc_stage_pool()
2481 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); in i915_guc_stage_pool()
2482 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); in i915_guc_stage_pool()
2483 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); in i915_guc_stage_pool()
2484 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); in i915_guc_stage_pool()
2520 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", in i915_guc_log_dump()
2633 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); in i915_psr_sink_status_show()
2665 seq_printf(m, "Source PSR status: 0x%x [%s]\n", in psr_source_status()
2684 seq_printf(m, "Source PSR status: 0x%x [%s]\n", in psr_source_status()
2690 seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown"); in psr_source_status()
2704 seq_printf(m, "Sink_Support: %s\n", yesno(sink_support)); in i915_edp_psr_status()
2711 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); in i915_edp_psr_status()
2712 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", in i915_edp_psr_status()
2720 seq_printf(m, "Main link in standby mode: %s\n", in i915_edp_psr_status()
2723 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); in i915_edp_psr_status()
2732 seq_printf(m, "Performance_Counter: %u\n", psrperf); in i915_edp_psr_status()
2739 seq_printf(m, "Last attempted entry at: %lld\n", in i915_edp_psr_status()
2741 seq_printf(m, "Last exit at: %lld\n", in i915_edp_psr_status()
2804 seq_printf(m, "%llu", power); in i915_energy_uJ()
2817 seq_printf(m, "GPU idle: %s (epoch %u)\n", in i915_runtime_pm_status()
2819 seq_printf(m, "IRQs disabled: %s\n", in i915_runtime_pm_status()
2822 seq_printf(m, "Usage count: %d\n", in i915_runtime_pm_status()
2825 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); in i915_runtime_pm_status()
2827 seq_printf(m, "PCI device power state: %s [%d]\n", in i915_runtime_pm_status()
2842 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); in i915_power_domain_info()
2848 seq_printf(m, "%-25s %d\n", power_well->name, in i915_power_domain_info()
2852 seq_printf(m, " %-23s %d\n", in i915_power_domain_info()
2874 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); in i915_dmc_info()
2875 seq_printf(m, "path: %s\n", csr->fw_path); in i915_dmc_info()
2880 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), in i915_dmc_info()
2885 seq_printf(m, "DC3 -> DC5 count: %d\n", in i915_dmc_info()
2887 seq_printf(m, "DC5 -> DC6 count: %d\n", in i915_dmc_info()
2890 seq_printf(m, "DC3 -> DC5 count: %d\n", in i915_dmc_info()
2895 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); in i915_dmc_info()
2896 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); in i915_dmc_info()
2897 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); in i915_dmc_info()
2912 …seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d… in intel_seq_print_mode()
2933 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", in intel_encoder_info()
2937 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", in intel_encoder_info()
2943 seq_printf(m, ", mode:\n"); in intel_encoder_info()
2961 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", in intel_crtc_info()
2974 seq_printf(m, "\tfixed mode:\n"); in intel_panel_info()
2984 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_info()
2985 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); in intel_dp_info()
3004 seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); in intel_dp_mst_info()
3013 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); in intel_hdmi_info()
3029 seq_printf(m, "connector %d: type %s, status: %s\n", in intel_connector_info()
3033 seq_printf(m, "\tname: %s\n", connector->display_info.name); in intel_connector_info()
3034 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", in intel_connector_info()
3037 seq_printf(m, "\tsubpixel order: %s\n", in intel_connector_info()
3039 seq_printf(m, "\tCEA rev: %d\n", in intel_connector_info()
3067 seq_printf(m, "\tmodes:\n"); in intel_connector_info()
3135 …seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%… in intel_plane_info()
3163 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", in intel_scaler_info()
3172 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", in intel_scaler_info()
3190 seq_printf(m, "CRTC info\n"); in i915_display_info()
3191 seq_printf(m, "---------\n"); in i915_display_info()
3198 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", in i915_display_info()
3210 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", in i915_display_info()
3221 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", in i915_display_info()
3227 seq_printf(m, "\n"); in i915_display_info()
3228 seq_printf(m, "Connector info\n"); in i915_display_info()
3229 seq_printf(m, "--------------\n"); in i915_display_info()
3251 seq_printf(m, "GT awake? %s (epoch %u)\n", in i915_engine_info()
3253 seq_printf(m, "Global active requests: %d\n", in i915_engine_info()
3255 seq_printf(m, "CS timestamp frequency: %u kHz\n", in i915_engine_info()
3281 seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks); in i915_shrinker_info()
3282 seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch); in i915_shrinker_info()
3297 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, in i915_shared_dplls_info()
3299 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", in i915_shared_dplls_info()
3301 seq_printf(m, " tracked hardware state:\n"); in i915_shared_dplls_info()
3302 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); in i915_shared_dplls_info()
3303 seq_printf(m, " dpll_md: 0x%08x\n", in i915_shared_dplls_info()
3305 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); in i915_shared_dplls_info()
3306 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); in i915_shared_dplls_info()
3307 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); in i915_shared_dplls_info()
3308 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
3309 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()
3310 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", in i915_shared_dplls_info()
3312 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", in i915_shared_dplls_info()
3314 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", in i915_shared_dplls_info()
3316 seq_printf(m, " mg_pll_div0: 0x%08x\n", in i915_shared_dplls_info()
3318 seq_printf(m, " mg_pll_div1: 0x%08x\n", in i915_shared_dplls_info()
3320 seq_printf(m, " mg_pll_lf: 0x%08x\n", in i915_shared_dplls_info()
3322 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", in i915_shared_dplls_info()
3324 seq_printf(m, " mg_pll_ssc: 0x%08x\n", in i915_shared_dplls_info()
3326 seq_printf(m, " mg_pll_bias: 0x%08x\n", in i915_shared_dplls_info()
3328 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", in i915_shared_dplls_info()
3341 seq_printf(m, "Workarounds applied: %d\n", wa->count); in i915_wa_registers()
3343 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", in i915_wa_registers()
3353 seq_printf(m, "Isochronous Priority Control: %s\n", in i915_ipc_status_show()
3416 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); in i915_ddb_info()
3419 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); in i915_ddb_info()
3423 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, in i915_ddb_info()
3429 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, in i915_ddb_info()
3453 seq_printf(m, "%s:\n", connector->name); in drrs_status_per_crtc()
3486 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", in drrs_status_per_crtc()
3497 seq_printf(m, "DRRS_State: Unknown(%d)\n", in drrs_status_per_crtc()
3502 seq_printf(m, "\t\tVrefresh: %d", vrefresh); in drrs_status_per_crtc()
3524 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); in i915_drrs_status()
3559 seq_printf(m, "MST Source Port %c\n", in i915_dp_mst_info()
3701 seq_printf(m, "%lx", in i915_displayport_test_data_show()
3705 seq_printf(m, "hdisplay: %d\n", in i915_displayport_test_data_show()
3707 seq_printf(m, "vdisplay: %d\n", in i915_displayport_test_data_show()
3709 seq_printf(m, "bpc: %u\n", in i915_displayport_test_data_show()
3743 seq_printf(m, "%02lx", intel_dp->compliance.test_type); in i915_displayport_test_type_show()
3786 seq_printf(m, "WM%d %u (%u.%u usec)\n", in wm_latency_show()
4419 seq_printf(m, " %s Slice Mask: %04x\n", type, in i915_print_sseu_info()
4421 seq_printf(m, " %s Slice Total: %u\n", type, in i915_print_sseu_info()
4423 seq_printf(m, " %s Subslice Total: %u\n", type, in i915_print_sseu_info()
4426 seq_printf(m, " %s Slice%i subslices: %u\n", type, in i915_print_sseu_info()
4429 seq_printf(m, " %s EU Total: %u\n", type, in i915_print_sseu_info()
4431 seq_printf(m, " %s EU Per Subslice: %u\n", type, in i915_print_sseu_info()
4437 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); in i915_print_sseu_info()
4439 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); in i915_print_sseu_info()
4441 seq_printf(m, " Has Slice Power Gating: %s\n", in i915_print_sseu_info()
4443 seq_printf(m, " Has Subslice Power Gating: %s\n", in i915_print_sseu_info()
4445 seq_printf(m, " Has EU Power Gating: %s\n", in i915_print_sseu_info()
4523 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); in i915_hpd_storm_ctl_show()
4524 seq_printf(m, "Detected: %s\n", in i915_hpd_storm_ctl_show()
4857 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); in i915_dpcd_show()
4873 seq_printf(m, "Panel power up delay: %d\n", in i915_panel_show()
4875 seq_printf(m, "Panel power down delay: %d\n", in i915_panel_show()
4877 seq_printf(m, "Backlight on delay: %d\n", in i915_panel_show()
4879 seq_printf(m, "Backlight off delay: %d\n", in i915_panel_show()