Lines Matching refs:REG32
518 #define REG32(_reg, ...) \ macro
552 REG32(GEN7_3DPRIM_END_OFFSET),
553 REG32(GEN7_3DPRIM_START_VERTEX),
554 REG32(GEN7_3DPRIM_VERTEX_COUNT),
555 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
556 REG32(GEN7_3DPRIM_START_INSTANCE),
557 REG32(GEN7_3DPRIM_BASE_VERTEX),
558 REG32(GEN7_GPGPU_DISPATCHDIMX),
559 REG32(GEN7_GPGPU_DISPATCHDIMY),
560 REG32(GEN7_GPGPU_DISPATCHDIMZ),
570 REG32(GEN7_SO_WRITE_OFFSET(0)),
571 REG32(GEN7_SO_WRITE_OFFSET(1)),
572 REG32(GEN7_SO_WRITE_OFFSET(2)),
573 REG32(GEN7_SO_WRITE_OFFSET(3)),
574 REG32(GEN7_L3SQCREG1),
575 REG32(GEN7_L3CNTLREG2),
576 REG32(GEN7_L3CNTLREG3),
597 REG32(HSW_SCRATCH1,
600 REG32(HSW_ROW_CHICKEN3,
609 REG32(BCS_SWCTRL),
614 REG32(FORCEWAKE_MT),
615 REG32(DERRMR),
616 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
617 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
618 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
622 REG32(FORCEWAKE_MT),
623 REG32(DERRMR),
627 #undef REG32