374 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;  in pch_pp_control_mmio_write()
375 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;  in pch_pp_control_mmio_write()
376 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;  in pch_pp_control_mmio_write()
377 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;  in pch_pp_control_mmio_write()
380 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=  in pch_pp_control_mmio_write()
543 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))  in ddi_buf_ctl_mmio_write()
561 	u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));  in fdi_auto_training_started()
563 	u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));  in fdi_auto_training_started()
604 	if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)  in check_fdi_rx_train_status()
607 	if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)  in check_fdi_rx_train_status()
609 		&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)  in check_fdi_rx_train_status()
666 		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;  in update_fdi_rx_iir_status()
672 		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;  in update_fdi_rx_iir_status()
676 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=  in update_fdi_rx_iir_status()
697 		vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);  in dp_tp_ctl_mmio_write()
761 	vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);  in pri_surf_mmio_write()
782 	vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);  in spr_surf_mmio_write()
1110 	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>  in sbi_data_mmio_read()
1112 		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &  in sbi_data_mmio_read()
1137 	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>  in sbi_ctl_mmio_write()
1139 		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &  in sbi_ctl_mmio_write()
1143 					   vgpu_vreg_t(vgpu, SBI_DATA));  in sbi_ctl_mmio_write()
1403 	u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);  in mailbox_write()
1592 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=  in bxt_gt_disp_pwron_write()
1594 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=  in bxt_gt_disp_pwron_write()
1599 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=  in bxt_gt_disp_pwron_write()
1601 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=  in bxt_gt_disp_pwron_write()