62 	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))  in edp_pipe_is_enabled()
77 	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)  in pipe_is_enabled()
175 		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |  in emulate_monitor_status_change()
180 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
185 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
190 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
197 	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |  in emulate_monitor_status_change()
202 		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |  in emulate_monitor_status_change()
204 		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=  in emulate_monitor_status_change()
209 		vgpu_vreg_t(vgpu, LCPLL1_CTL) |=  in emulate_monitor_status_change()
212 		vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;  in emulate_monitor_status_change()
217 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;  in emulate_monitor_status_change()
218 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
221 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
226 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=  in emulate_monitor_status_change()
228 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=  in emulate_monitor_status_change()
231 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;  in emulate_monitor_status_change()
232 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
233 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;  in emulate_monitor_status_change()
237 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;  in emulate_monitor_status_change()
238 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
241 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
246 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=  in emulate_monitor_status_change()
248 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=  in emulate_monitor_status_change()
251 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;  in emulate_monitor_status_change()
252 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
253 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;  in emulate_monitor_status_change()
257 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;  in emulate_monitor_status_change()
258 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
261 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
266 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=  in emulate_monitor_status_change()
268 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=  in emulate_monitor_status_change()
271 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;  in emulate_monitor_status_change()
272 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
273 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;  in emulate_monitor_status_change()
278 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;  in emulate_monitor_status_change()
283 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
286 			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;  in emulate_monitor_status_change()
288 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;  in emulate_monitor_status_change()
293 		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;  in emulate_monitor_status_change()
297 		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;  in emulate_monitor_status_change()
298 		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;  in emulate_monitor_status_change()
299 		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;  in emulate_monitor_status_change()
300 		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;  in emulate_monitor_status_change()
303 	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;  in emulate_monitor_status_change()
407 		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;  in emulate_vblank_on_pipe()
412 		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;  in emulate_vblank_on_pipe()