Lines Matching refs:lane_value
232 u32 lane_reg, lane_value; in cdv_dpll_set_clock_cdv() local
346 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
347 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
348 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
349 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
352 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
353 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
354 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
355 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
358 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
359 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
360 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
361 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
364 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
365 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
366 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
367 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()