121 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {  in drm_dp_link_train_clock_recovery_delay()
122 	int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_link_train_clock_recovery_delay()
129 	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)  in drm_dp_link_train_clock_recovery_delay()
136 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {  in drm_dp_link_train_channel_eq_delay()
137 	int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_link_train_channel_eq_delay()
496 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_clock()
500 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_downstream_max_clock()
527 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_bpc()
531 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_downstream_max_bpc()
583 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_debug()
586 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_downstream_debug()
594 	bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_downstream_debug()
643 		clk = drm_dp_downstream_max_clock(dpcd, port_cap);  in drm_dp_downstream_debug()
652 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);  in drm_dp_downstream_debug()