Lines Matching refs:I2C_IDX_RX_P0

44 #define I2C_IDX_RX_P0		3  macro
55 [I2C_IDX_RX_P0] = RX_P0,
265 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_set_hpd()
287 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_clear_hpd()
309 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, in anx78xx_rx_initialization()
314 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG, in anx78xx_rx_initialization()
320 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
326 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
333 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
339 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
345 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG, in anx78xx_rx_initialization()
350 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
367 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_rx_initialization()
451 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_xtal_clk_sel()
457 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_xtal_clk_sel()
605 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG, in anx78xx_enable_interrupts()
753 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, in anx78xx_dp_link_training()
1213 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, in anx78xx_handle_hdmi_int_1()
1223 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_handle_hdmi_int_1()
1280 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, in anx78xx_intp_threaded_handler()