113 u32 ast_mindwm(struct ast_private *ast, u32 r)  in ast_mindwm()  function
173 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;  in mmctestburst2_ast2150()
183 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;  in mmctestburst2_ast2150()
189 	data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;  in mmctestburst2_ast2150()
203 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
209 	data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
457 		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;  in mmc_test()
477 		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;  in mmc_test2()
483 	data = ast_mindwm(ast, 0x1e6e0078);  in mmc_test2()
723 	reg_mcr0c  = ast_mindwm(ast, 0x1E6E000C);  in finetuneDQSI()
724 	reg_mcr18  = ast_mindwm(ast, 0x1E6E0018);  in finetuneDQSI()
856 	ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));  in cbr_dll2()
867 	trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;  in get_ddr3_info()
1144 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1146 	data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1149 		data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;  in ddr3_init()
1159 		data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;  in ddr3_init()
1164 		ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);  in ddr3_init()
1166 		data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;  in ddr3_init()
1171 			data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1174 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr3_init()
1177 	ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);  in ddr3_init()
1178 	data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;  in ddr3_init()
1215 		data = ast_mindwm(ast, 0x1E6E0070);  in ddr3_init()
1232 	trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;  in get_ddr2_info()
1513 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1515 	data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1518 		data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;  in ddr2_init()
1528 		data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;  in ddr2_init()
1533 		ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);  in ddr2_init()
1535 		data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;  in ddr2_init()
1540 			data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1543 		data = ast_mindwm(ast, 0x1E6E001C);  in ddr2_init()
1546 	ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);  in ddr2_init()
1547 	data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;  in ddr2_init()
1589 		data = ast_mindwm(ast, 0x1E6E0070);  in ddr2_init()
1626 		temp = ast_mindwm(ast, 0x1e6e2070);  in ast_post_chip_2300()
1671 		temp = ast_mindwm(ast, 0x1e6e2040);  in ast_post_chip_2300()
1740 			data = ast_mindwm(ast, 0x1E6E0060) & 0x1;  in ddr_phy_init_2500()
1745 			data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;  in ddr_phy_init_2500()
1770 	reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;  in check_dram_size_2500()
1771 	reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;  in check_dram_size_2500()
1779 	if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {  in check_dram_size_2500()
1783 	} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {  in check_dram_size_2500()
1787 	} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {  in check_dram_size_2500()
1801 	reg_04 = ast_mindwm(ast, 0x1E6E0004);  in enable_cache_2500()
1805 		data = ast_mindwm(ast, 0x1E6E0004);  in enable_cache_2500()
1824 	data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;  in set_mpll_2500()
1944 				data = ast_mindwm(ast, 0x1E6E03D0);  in ddr4_init_2500()
2014 		data = ast_mindwm(ast, 0x1E6E2070);  in ast_dram_init_2500()
2021 	ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);  in ast_dram_init_2500()
2024 	data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;  in ast_dram_init_2500()
2060 		temp  = ast_mindwm(ast, 0x1e6e2094);  in ast_post_chip_2500()
2063 		temp  = ast_mindwm(ast, 0x1e6e2070);  in ast_post_chip_2500()
2073 		temp = ast_mindwm(ast, 0x1e6e2040);  in ast_post_chip_2500()