38 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)  in smu7_set_smc_sram_address()  argument
43 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);  in smu7_set_smc_sram_address()
44 …PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_A…  in smu7_set_smc_sram_address()
49 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, ui…  in smu7_copy_bytes_from_smc()  argument
63 		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);  in smu7_copy_bytes_from_smc()
73 		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);  in smu7_copy_bytes_from_smc()
85 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,  in smu7_copy_bytes_to_smc()  argument
103 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);  in smu7_copy_bytes_to_smc()
108 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);  in smu7_copy_bytes_to_smc()
119 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);  in smu7_copy_bytes_to_smc()
125 		original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);  in smu7_copy_bytes_to_smc()
139 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);  in smu7_copy_bytes_to_smc()
144 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);  in smu7_copy_bytes_to_smc()
151 int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)  in smu7_program_jump_on_start()  argument
155 	smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);  in smu7_program_jump_on_start()
160 bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)  in smu7_is_smc_ram_running()  argument
162 …return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_…  in smu7_is_smc_ram_running()
163 	&& (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));  in smu7_is_smc_ram_running()
166 int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)  in smu7_send_msg_to_smc()  argument
170 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc()
172 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);  in smu7_send_msg_to_smc()
179 	cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);  in smu7_send_msg_to_smc()
180 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);  in smu7_send_msg_to_smc()
182 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc()
184 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);  in smu7_send_msg_to_smc()
194 int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)  in smu7_send_msg_to_smc_without_waiting()  argument
196 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);  in smu7_send_msg_to_smc_without_waiting()
201 int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)  in smu7_send_msg_to_smc_with_parameter()  argument
203 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc_with_parameter()
205 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);  in smu7_send_msg_to_smc_with_parameter()
207 	return smu7_send_msg_to_smc(hwmgr, msg);  in smu7_send_msg_to_smc_with_parameter()
210 int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint3…  in smu7_send_msg_to_smc_with_parameter_without_waiting()  argument
212 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);  in smu7_send_msg_to_smc_with_parameter_without_waiting()
214 	return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);  in smu7_send_msg_to_smc_with_parameter_without_waiting()
217 int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)  in smu7_send_msg_to_smc_offset()  argument
219 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);  in smu7_send_msg_to_smc_offset()
221 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);  in smu7_send_msg_to_smc_offset()
223 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);  in smu7_send_msg_to_smc_offset()
225 	if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))  in smu7_send_msg_to_smc_offset()
280 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t l…  in smu7_read_smc_sram_dword()  argument
284 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);  in smu7_read_smc_sram_dword()
286 	*value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);  in smu7_read_smc_sram_dword()
291 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t l…  in smu7_write_smc_sram_dword()  argument
295 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);  in smu7_write_smc_sram_dword()
300 	cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);  in smu7_write_smc_sram_dword()
343 static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,  in smu7_populate_single_firmware_entry()  argument
350 	result = cgs_get_firmware_info(hwmgr->device,  in smu7_populate_single_firmware_entry()
363 		if (!hwmgr->not_vf)  in smu7_populate_single_firmware_entry()
378 int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)  in smu7_request_smu_load_fw()  argument
380 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_request_smu_load_fw()
384 	if (!hwmgr->reload_fw) {  in smu7_request_smu_load_fw()
390 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,  in smu7_request_smu_load_fw()
391 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,  in smu7_request_smu_load_fw()
395 	if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */  in smu7_request_smu_load_fw()
396 		if (hwmgr->not_vf) {  in smu7_request_smu_load_fw()
397 			smu7_send_msg_to_smc_with_parameter(hwmgr,  in smu7_request_smu_load_fw()
400 			smu7_send_msg_to_smc_with_parameter(hwmgr,  in smu7_request_smu_load_fw()
433 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
436 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
439 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
442 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
445 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
448 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
451 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
454 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
457 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
460 		if (!hwmgr->not_vf)  in smu7_request_smu_load_fw()
461 			PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,  in smu7_request_smu_load_fw()
467 …smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->hea…  in smu7_request_smu_load_fw()
468 …smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->hea…  in smu7_request_smu_load_fw()
470 	if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))  in smu7_request_smu_load_fw()
482 int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)  in smu7_check_fw_load_finish()  argument
484 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_check_fw_load_finish()
488 	ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,  in smu7_check_fw_load_finish()
489 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,  in smu7_check_fw_load_finish()
495 int smu7_reload_firmware(struct pp_hwmgr *hwmgr)  in smu7_reload_firmware()  argument
497 	return hwmgr->smumgr_funcs->start_smu(hwmgr);  in smu7_reload_firmware()
500 static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, ui…  in smu7_upload_smc_firmware_data()  argument
506 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);  in smu7_upload_smc_firmware_data()
507 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);  in smu7_upload_smc_firmware_data()
510 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);  in smu7_upload_smc_firmware_data()
512 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);  in smu7_upload_smc_firmware_data()
520 int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)  in smu7_upload_smu_firmware_image()  argument
523 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_upload_smu_firmware_image()
528 		cgs_get_firmware_info(hwmgr->device,  in smu7_upload_smu_firmware_image()
531 		cgs_get_firmware_info(hwmgr->device,  in smu7_upload_smu_firmware_image()
534 	hwmgr->is_kicker = info.is_kicker;  in smu7_upload_smu_firmware_image()
535 	hwmgr->smu_version = info.version;  in smu7_upload_smu_firmware_image()
536 …result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZ…  in smu7_upload_smu_firmware_image()
541 static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)  in execute_pwr_table()  argument
550 			cgs_write_register(hwmgr->device, reg, data);  in execute_pwr_table()
557 static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)  in execute_pwr_dfy_table()  argument
561 	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);  in execute_pwr_dfy_table()
562 	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);  in execute_pwr_dfy_table()
563 	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);  in execute_pwr_dfy_table()
565 		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);  in execute_pwr_dfy_table()
568 int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)  in smu7_setup_pwr_virus()  argument
570 	execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));  in smu7_setup_pwr_virus()
571 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);  in smu7_setup_pwr_virus()
572 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);  in smu7_setup_pwr_virus()
573 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);  in smu7_setup_pwr_virus()
574 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);  in smu7_setup_pwr_virus()
575 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);  in smu7_setup_pwr_virus()
576 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);  in smu7_setup_pwr_virus()
577 	execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));  in smu7_setup_pwr_virus()
582 int smu7_init(struct pp_hwmgr *hwmgr)  in smu7_init()  argument
587 	smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_init()
593 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,  in smu7_init()
604 	if (!hwmgr->not_vf)  in smu7_init()
608 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,  in smu7_init()
623 	if (smum_is_hw_avfs_present(hwmgr))  in smu7_init()
624 		hwmgr->avfs_supported = true;  in smu7_init()
630 int smu7_smu_fini(struct pp_hwmgr *hwmgr)  in smu7_smu_fini()  argument
632 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);  in smu7_smu_fini()
638 	if (hwmgr->not_vf)  in smu7_smu_fini()
646 	kfree(hwmgr->smu_backend);  in smu7_smu_fini()
647 	hwmgr->smu_backend = NULL;  in smu7_smu_fini()