Lines Matching refs:hwmgr
93 static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr, in ci_set_smc_sram_address() argument
102 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
103 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
107 static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, in ci_copy_bytes_to_smc() argument
128 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
133 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
144 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
150 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
164 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
169 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
176 static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr) in ci_program_jump_on_start() argument
180 ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1); in ci_program_jump_on_start()
185 bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr) in ci_is_smc_ram_running() argument
187 return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, in ci_is_smc_ram_running()
189 && (0x20100 <= cgs_read_ind_register(hwmgr->device, in ci_is_smc_ram_running()
193 static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, in ci_read_smc_sram_dword() argument
198 result = ci_set_smc_sram_address(hwmgr, smc_addr, limit); in ci_read_smc_sram_dword()
203 *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_read_smc_sram_dword()
207 static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) in ci_send_msg_to_smc() argument
211 cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0); in ci_send_msg_to_smc()
212 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); in ci_send_msg_to_smc()
214 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); in ci_send_msg_to_smc()
216 ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); in ci_send_msg_to_smc()
224 static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, in ci_send_msg_to_smc_with_parameter() argument
227 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter); in ci_send_msg_to_smc_with_parameter()
228 return ci_send_msg_to_smc(hwmgr, msg); in ci_send_msg_to_smc_with_parameter()
231 static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) in ci_initialize_power_tune_defaults() argument
233 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_initialize_power_tune_defaults()
234 struct amdgpu_device *adev = hwmgr->adev; in ci_initialize_power_tune_defaults()
274 static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, in ci_get_dependency_volt_by_clk() argument
294 static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr, in ci_calculate_sclk_params() argument
297 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_calculate_sclk_params()
310 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in ci_calculate_sclk_params()
317 ref_clock = atomctrl_get_reference_clock(hwmgr); in ci_calculate_sclk_params()
337 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_calculate_sclk_params()
342 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr, in ci_calculate_sclk_params()
368 static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, in ci_populate_phase_value_based_on_sclk() argument
405 static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr, in ci_populate_single_graphic_level() argument
409 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_single_graphic_level()
412 result = ci_calculate_sclk_params(hwmgr, clock, level); in ci_populate_single_graphic_level()
415 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_graphic_level()
416 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
427 ci_populate_phase_value_based_on_sclk(hwmgr, in ci_populate_single_graphic_level()
428 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
444 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_populate_single_graphic_level()
469 static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) in ci_populate_all_graphic_levels() argument
471 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_all_graphic_levels()
472 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_all_graphic_levels()
484 result = ci_populate_single_graphic_level(hwmgr, in ci_populate_all_graphic_levels()
502 result = ci_copy_bytes_to_smc(hwmgr, array, in ci_populate_all_graphic_levels()
510 static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr) in ci_populate_svi_load_line() argument
512 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_svi_load_line()
523 static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr) in ci_populate_tdc_limit() argument
526 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_tdc_limit()
529 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in ci_populate_tdc_limit()
539 static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) in ci_populate_dw8() argument
541 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_dw8()
545 if (ci_read_smc_sram_dword(hwmgr, in ci_populate_dw8()
558 static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) in ci_populate_fuzzy_fan() argument
561 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_fuzzy_fan()
563 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) in ci_populate_fuzzy_fan()
564 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) in ci_populate_fuzzy_fan()
565 tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity; in ci_populate_fuzzy_fan()
567 tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; in ci_populate_fuzzy_fan()
574 static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) in ci_populate_bapm_vddc_vid_sidd() argument
577 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_bapm_vddc_vid_sidd()
582 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
584 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
586 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
589 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in ci_populate_bapm_vddc_vid_sidd()
590 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) { in ci_populate_bapm_vddc_vid_sidd()
591 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in ci_populate_bapm_vddc_vid_sidd()
592 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in ci_populate_bapm_vddc_vid_sidd()
593 hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); in ci_populate_bapm_vddc_vid_sidd()
595 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc); in ci_populate_bapm_vddc_vid_sidd()
596 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage); in ci_populate_bapm_vddc_vid_sidd()
603 static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr) in ci_populate_vddc_vid() argument
606 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_vddc_vid()
608 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_vddc_vid()
620 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr) in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() argument
622 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
652 static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) in ci_populate_bapm_vddc_base_leakage_sidd() argument
654 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_bapm_vddc_base_leakage_sidd()
657 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
670 static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) in ci_populate_pm_fuses() argument
672 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_pm_fuses()
676 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_populate_pm_fuses()
678 if (ci_read_smc_sram_dword(hwmgr, in ci_populate_pm_fuses()
687 ret = ci_populate_bapm_vddc_vid_sidd(hwmgr); in ci_populate_pm_fuses()
689 ret |= ci_populate_vddc_vid(hwmgr); in ci_populate_pm_fuses()
691 ret |= ci_populate_svi_load_line(hwmgr); in ci_populate_pm_fuses()
693 ret |= ci_populate_tdc_limit(hwmgr); in ci_populate_pm_fuses()
695 ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset); in ci_populate_pm_fuses()
697 ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset); in ci_populate_pm_fuses()
699 ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr); in ci_populate_pm_fuses()
701 ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr); in ci_populate_pm_fuses()
705 ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, in ci_populate_pm_fuses()
712 static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) in ci_populate_bapm_parameters_in_dpm_table() argument
714 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_bapm_parameters_in_dpm_table()
715 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_bapm_parameters_in_dpm_table()
718 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; in ci_populate_bapm_parameters_in_dpm_table()
719 struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; in ci_populate_bapm_parameters_in_dpm_table()
761 static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr, in ci_get_std_voltage_value_sidd() argument
770 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
774 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in ci_get_std_voltage_value_sidd()
779 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
780 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
782 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { in ci_get_std_voltage_value_sidd()
783 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
784 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); in ci_get_std_voltage_value_sidd()
787 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
788 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in ci_get_std_voltage_value_sidd()
795 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
796 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
798 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { in ci_get_std_voltage_value_sidd()
799 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
800 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
803 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
804 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in ci_get_std_voltage_value_sidd()
817 static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_voltage_table() argument
823 result = ci_get_std_voltage_value_sidd(hwmgr, tab, in ci_populate_smc_voltage_table()
838 static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_vddc_table() argument
843 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_vddc_table()
847 result = ci_populate_smc_voltage_table(hwmgr, in ci_populate_smc_vddc_table()
867 static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_vdd_ci_table() argument
870 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_vdd_ci_table()
877 result = ci_populate_smc_voltage_table(hwmgr, in ci_populate_smc_vdd_ci_table()
895 static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, in ci_populate_smc_mvdd_table() argument
898 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_mvdd_table()
905 result = ci_populate_smc_voltage_table(hwmgr, in ci_populate_smc_mvdd_table()
924 static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, in ci_populate_smc_voltage_tables() argument
929 result = ci_populate_smc_vddc_table(hwmgr, table); in ci_populate_smc_voltage_tables()
933 result = ci_populate_smc_vdd_ci_table(hwmgr, table); in ci_populate_smc_voltage_tables()
937 result = ci_populate_smc_mvdd_table(hwmgr, table); in ci_populate_smc_voltage_tables()
944 static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr, in ci_populate_ulv_level() argument
949 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_ulv_level()
954 result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage); in ci_populate_ulv_level()
964 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
968 …state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltag… in ci_populate_ulv_level()
971 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
975 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in ci_populate_ulv_level()
988 static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr, in ci_populate_ulv_state() argument
991 return ci_populate_ulv_level(hwmgr, ulv_level); in ci_populate_ulv_state()
994 static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
996 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_link_level()
998 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_smc_link_level()
1021 struct pp_hwmgr *hwmgr, in ci_calculate_mclk_params() argument
1028 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_calculate_mclk_params()
1042 result = atomctrl_get_memory_pll_dividers_si(hwmgr, in ci_calculate_mclk_params()
1066 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_calculate_mclk_params()
1071 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); in ci_calculate_mclk_params()
1083 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { in ci_calculate_mclk_params()
1154 static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_she… in ci_populate_phase_value_based_on_mclk() argument
1172 struct pp_hwmgr *hwmgr, in ci_populate_single_memory_level() argument
1177 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_single_memory_level()
1184 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { in ci_populate_single_memory_level()
1185 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_memory_level()
1186 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
1191 if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { in ci_populate_single_memory_level()
1192 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_memory_level()
1193 hwmgr->dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
1200 if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { in ci_populate_single_memory_level()
1201 result = ci_get_dependency_volt_by_clk(hwmgr, in ci_populate_single_memory_level()
1202 hwmgr->dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
1212 ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_memory_level()
1233 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()
1258 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) in ci_populate_single_memory_level()
1259 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1261 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1267 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1270 result = ci_calculate_mclk_params(hwmgr, in ci_populate_single_memory_level()
1296 static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) in ci_populate_all_memory_levels() argument
1298 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_all_memory_levels()
1299 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_all_memory_levels()
1302 struct amdgpu_device *adev = hwmgr->adev; in ci_populate_all_memory_levels()
1315 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1339 result = ci_copy_bytes_to_smc(hwmgr, in ci_populate_all_memory_levels()
1346 static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, in ci_populate_mvdd_value() argument
1349 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_mvdd_value()
1355 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { in ci_populate_mvdd_value()
1356 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { in ci_populate_mvdd_value()
1363 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, in ci_populate_mvdd_value()
1373 static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_acpi_level() argument
1377 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_acpi_level()
1397 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); in ci_populate_smc_acpi_level()
1400 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, in ci_populate_smc_acpi_level()
1454 if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level)) in ci_populate_smc_acpi_level()
1514 static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_uvd_level() argument
1521 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in ci_populate_smc_uvd_level()
1534 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_uvd_level()
1541 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_uvd_level()
1555 static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_vce_level() argument
1562 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in ci_populate_smc_vce_level()
1573 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_vce_level()
1587 static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_acp_level() argument
1594 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in ci_populate_smc_acp_level()
1604 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, in ci_populate_smc_acp_level()
1618 struct pp_hwmgr *hwmgr, in ci_populate_memory_timing_parameters() argument
1629 result = atomctrl_set_engine_dram_timings_rv770(hwmgr, in ci_populate_memory_timing_parameters()
1635 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); in ci_populate_memory_timing_parameters()
1636 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); in ci_populate_memory_timing_parameters()
1637 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); in ci_populate_memory_timing_parameters()
1646 static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) in ci_program_memory_timing_parameters() argument
1648 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_program_memory_timing_parameters()
1649 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_program_memory_timing_parameters()
1659 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1670 hwmgr, in ci_program_memory_timing_parameters()
1681 static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, in ci_populate_smc_boot_level() argument
1685 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_boot_level()
1686 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_smc_boot_level()
1719 static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr, in ci_populate_mc_reg_address() argument
1722 const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend; in ci_populate_mc_reg_address()
1759 struct pp_hwmgr *hwmgr, in ci_convert_mc_reg_table_entry_to_smc() argument
1764 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_convert_mc_reg_table_entry_to_smc()
1784 static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, in ci_convert_mc_reg_table_to_smc() argument
1788 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_convert_mc_reg_table_to_smc()
1794 hwmgr, in ci_convert_mc_reg_table_to_smc()
1806 static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) in ci_update_and_upload_mc_reg_table() argument
1808 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_update_and_upload_mc_reg_table()
1809 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_update_and_upload_mc_reg_table()
1819 result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs)); in ci_update_and_upload_mc_reg_table()
1826 return ci_copy_bytes_to_smc(hwmgr, address, in ci_update_and_upload_mc_reg_table()
1832 static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) in ci_populate_initial_mc_reg_table() argument
1835 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_initial_mc_reg_table()
1838 result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); in ci_populate_initial_mc_reg_table()
1842 result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs); in ci_populate_initial_mc_reg_table()
1846 return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
1850 static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr) in ci_populate_smc_initial_state() argument
1852 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_initial_state()
1853 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_populate_smc_initial_state()
1856 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in ci_populate_smc_initial_state()
1859 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk in ci_populate_smc_initial_state()
1866 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); in ci_populate_smc_initial_state()
1869 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk in ci_populate_smc_initial_state()
1879 static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr, in ci_populate_smc_svi2_config() argument
1882 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_smc_svi2_config()
1891 static int ci_start_smc(struct pp_hwmgr *hwmgr) in ci_start_smc() argument
1894 ci_program_jump_on_start(hwmgr); in ci_start_smc()
1897 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); in ci_start_smc()
1899 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); in ci_start_smc()
1901 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, in ci_start_smc()
1907 static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_vr_config() argument
1909 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_populate_vr_config()
1938 static int ci_init_smc_table(struct pp_hwmgr *hwmgr) in ci_init_smc_table() argument
1941 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_init_smc_table()
1942 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_init_smc_table()
1947 ci_initialize_power_tune_defaults(hwmgr); in ci_init_smc_table()
1951 ci_populate_smc_voltage_tables(hwmgr, table); in ci_init_smc_table()
1953 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
1958 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
1966 result = ci_populate_ulv_state(hwmgr, &(table->Ulv)); in ci_init_smc_table()
1970 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in ci_init_smc_table()
1974 result = ci_populate_all_graphic_levels(hwmgr); in ci_init_smc_table()
1978 result = ci_populate_all_memory_levels(hwmgr); in ci_init_smc_table()
1982 result = ci_populate_smc_link_level(hwmgr, table); in ci_init_smc_table()
1986 result = ci_populate_smc_acpi_level(hwmgr, table); in ci_init_smc_table()
1990 result = ci_populate_smc_vce_level(hwmgr, table); in ci_init_smc_table()
1994 result = ci_populate_smc_acp_level(hwmgr, table); in ci_init_smc_table()
2000 result = ci_program_memory_timing_parameters(hwmgr); in ci_init_smc_table()
2004 result = ci_populate_smc_uvd_level(hwmgr, table); in ci_init_smc_table()
2016 result = ci_populate_smc_boot_level(hwmgr, table); in ci_init_smc_table()
2020 result = ci_populate_smc_initial_state(hwmgr); in ci_init_smc_table()
2023 result = ci_populate_bapm_parameters_in_dpm_table(hwmgr); in ci_init_smc_table()
2057 result = ci_populate_vr_config(hwmgr, table); in ci_init_smc_table()
2062 ci_populate_smc_svi2_config(hwmgr, table); in ci_init_smc_table()
2069 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { in ci_init_smc_table()
2071 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
2075 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_init_smc_table()
2099 result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start + in ci_init_smc_table()
2108 result = ci_populate_initial_mc_reg_table(hwmgr); in ci_init_smc_table()
2112 result = ci_populate_pm_fuses(hwmgr); in ci_init_smc_table()
2116 ci_start_smc(hwmgr); in ci_init_smc_table()
2121 static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) in ci_thermal_setup_fan_table() argument
2123 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_thermal_setup_fan_table()
2132 …if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl… in ci_thermal_setup_fan_table()
2135 if (hwmgr->thermal_controller.fanInfo.bNoFan) { in ci_thermal_setup_fan_table()
2136 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_thermal_setup_fan_table()
2142 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); in ci_thermal_setup_fan_table()
2146 …duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100… in ci_thermal_setup_fan_table()
2149 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); in ci_thermal_setup_fan_table()
2153 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100; in ci_thermal_setup_fan_table()
2157 …t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller… in ci_thermal_setup_fan_table()
2158 …t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controlle… in ci_thermal_setup_fan_table()
2160 …pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_contro… in ci_thermal_setup_fan_table()
2161 …pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_contr… in ci_thermal_setup_fan_table()
2166 …fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin… in ci_thermal_setup_fan_table()
2167 …fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed… in ci_thermal_setup_fan_table()
2168 …fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax… in ci_thermal_setup_fan_table()
2175 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst); in ci_thermal_setup_fan_table()
2183 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); in ci_thermal_setup_fan_table()
2185 …fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCyc… in ci_thermal_setup_fan_table()
2189 …fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT… in ci_thermal_setup_fan_table()
2191 …res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeo… in ci_thermal_setup_fan_table()
2196 static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) in ci_program_mem_timing_parameters() argument
2198 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_program_mem_timing_parameters()
2202 return ci_program_memory_timing_parameters(hwmgr); in ci_program_mem_timing_parameters()
2207 static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) in ci_update_sclk_threshold() argument
2209 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_update_sclk_threshold()
2210 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_update_sclk_threshold()
2215 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in ci_update_sclk_threshold()
2224 hwmgr, in ci_update_sclk_threshold()
2233 result = ci_update_and_upload_mc_reg_table(hwmgr); in ci_update_sclk_threshold()
2237 result = ci_program_mem_timing_parameters(hwmgr); in ci_update_sclk_threshold()
2304 static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr) in ci_load_smc_ucode() argument
2312 cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); in ci_load_smc_ucode()
2314 hwmgr->is_kicker = info.is_kicker; in ci_load_smc_ucode()
2315 hwmgr->smu_version = info.version; in ci_load_smc_ucode()
2325 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); in ci_load_smc_ucode()
2326 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); in ci_load_smc_ucode()
2330 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_load_smc_ucode()
2333 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_load_smc_ucode()
2343 static int ci_upload_firmware(struct pp_hwmgr *hwmgr) in ci_upload_firmware() argument
2345 if (ci_is_smc_ram_running(hwmgr)) { in ci_upload_firmware()
2349 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, in ci_upload_firmware()
2351 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL, in ci_upload_firmware()
2354 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); in ci_upload_firmware()
2355 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); in ci_upload_firmware()
2356 return ci_load_smc_ucode(hwmgr); in ci_upload_firmware()
2359 static int ci_process_firmware_header(struct pp_hwmgr *hwmgr) in ci_process_firmware_header() argument
2361 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_process_firmware_header()
2362 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_process_firmware_header()
2368 if (ci_upload_firmware(hwmgr)) in ci_process_firmware_header()
2371 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2381 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2393 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2401 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2411 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2421 result = ci_read_smc_sram_dword(hwmgr, in ci_process_firmware_header()
2427 hwmgr->microcode_version_info.SMC = tmp; in ci_process_firmware_header()
2434 static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr) in ci_get_memory_modile_index() argument
2436 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); in ci_get_memory_modile_index()
2574 static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, in ci_set_mc_special_registers() argument
2579 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_set_mc_special_registers()
2588 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); in ci_set_mc_special_registers()
2600 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); in ci_set_mc_special_registers()
2628 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); in ci_set_mc_special_registers()
2667 static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) in ci_initialize_mc_reg_table() argument
2670 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); in ci_initialize_mc_reg_table()
2673 uint8_t module_index = ci_get_memory_modile_index(hwmgr); in ci_initialize_mc_reg_table()
2681 …cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2682 …cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2683 …cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_… in ci_initialize_mc_reg_table()
2684 …cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2685 …cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2686 …cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2687 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_S… in ci_initialize_mc_reg_table()
2688 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_S… in ci_initialize_mc_reg_table()
2689 …cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_S… in ci_initialize_mc_reg_table()
2690 …cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2691 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2692 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_P… in ci_initialize_mc_reg_table()
2693 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2694 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2695 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2696 …cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2697 …cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2698 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SE… in ci_initialize_mc_reg_table()
2699 …cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_… in ci_initialize_mc_reg_table()
2700 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_… in ci_initialize_mc_reg_table()
2704 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); in ci_initialize_mc_reg_table()
2711 result = ci_set_mc_special_registers(hwmgr, ni_table); in ci_initialize_mc_reg_table()
2722 static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr) in ci_is_dpm_running() argument
2724 return ci_is_smc_ram_running(hwmgr); in ci_is_dpm_running()
2727 static int ci_smu_init(struct pp_hwmgr *hwmgr) in ci_smu_init() argument
2736 hwmgr->smu_backend = ci_priv; in ci_smu_init()
2741 static int ci_smu_fini(struct pp_hwmgr *hwmgr) in ci_smu_fini() argument
2743 kfree(hwmgr->smu_backend); in ci_smu_fini()
2744 hwmgr->smu_backend = NULL; in ci_smu_fini()
2748 static int ci_start_smu(struct pp_hwmgr *hwmgr) in ci_start_smu() argument
2753 static int ci_update_dpm_settings(struct pp_hwmgr *hwmgr, in ci_update_dpm_settings() argument
2756 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in ci_update_dpm_settings()
2758 (hwmgr->smu_backend); in ci_update_dpm_settings()
2779 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel); in ci_update_dpm_settings()
2788 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2790 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2802 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2805 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2809 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel); in ci_update_dpm_settings()
2814 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel); in ci_update_dpm_settings()
2823 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2825 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2837 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2840 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); in ci_update_dpm_settings()
2844 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel); in ci_update_dpm_settings()
2849 static int ci_update_uvd_smc_table(struct pp_hwmgr *hwmgr) in ci_update_uvd_smc_table() argument
2851 struct amdgpu_device *adev = hwmgr->adev; in ci_update_uvd_smc_table()
2852 struct smu7_hwmgr *data = hwmgr->backend; in ci_update_uvd_smc_table()
2853 struct ci_smumgr *smu_data = hwmgr->smu_backend; in ci_update_uvd_smc_table()
2855 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in ci_update_uvd_smc_table()
2860 uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : in ci_update_uvd_smc_table()
2861 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_uvd_smc_table()
2869 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475, in ci_update_uvd_smc_table()
2877 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_UVDDPM)) in ci_update_uvd_smc_table()
2880 ci_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask, in ci_update_uvd_smc_table()
2886 static int ci_update_vce_smc_table(struct pp_hwmgr *hwmgr) in ci_update_vce_smc_table() argument
2888 struct amdgpu_device *adev = hwmgr->adev; in ci_update_vce_smc_table()
2889 struct smu7_hwmgr *data = hwmgr->backend; in ci_update_vce_smc_table()
2891 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in ci_update_vce_smc_table()
2896 uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : in ci_update_vce_smc_table()
2897 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_vce_smc_table()
2900 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475, in ci_update_vce_smc_table()
2908 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_VCEDPM)) in ci_update_vce_smc_table()
2911 ci_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask, in ci_update_vce_smc_table()
2917 static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) in ci_update_smc_table() argument
2921 ci_update_uvd_smc_table(hwmgr); in ci_update_smc_table()
2924 ci_update_vce_smc_table(hwmgr); in ci_update_smc_table()