Lines Matching refs:hwmgr
50 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
52 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
57 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) in vega12_set_default_registry_data() argument
60 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_default_registry_data()
130 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) in vega12_set_features_platform_caps() argument
133 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_features_platform_caps()
134 struct amdgpu_device *adev = hwmgr->adev; in vega12_set_features_platform_caps()
137 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
140 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
143 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
147 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
149 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
154 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
164 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
166 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
170 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
180 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
182 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
189 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax) in vega12_set_features_platform_caps()
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
193 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
195 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
197 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
201 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
204 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
208 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
213 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
215 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
217 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
219 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
235 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); in vega12_set_features_platform_caps()
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); in vega12_set_features_platform_caps()
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); in vega12_set_features_platform_caps()
241 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); in vega12_set_features_platform_caps()
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); in vega12_set_features_platform_caps()
245 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); in vega12_set_features_platform_caps()
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); in vega12_set_features_platform_caps()
249 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); in vega12_set_features_platform_caps()
251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); in vega12_set_features_platform_caps()
254 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
265 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
267 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
269 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
274 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
277 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
282 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in vega12_set_features_platform_caps()
288 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) in vega12_init_dpm_defaults() argument
290 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_init_dpm_defaults()
357 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) in vega12_set_private_data_based_on_pptable() argument
362 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) in vega12_hwmgr_backend_fini() argument
364 kfree(hwmgr->backend); in vega12_hwmgr_backend_fini()
365 hwmgr->backend = NULL; in vega12_hwmgr_backend_fini()
370 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) in vega12_hwmgr_backend_init() argument
374 struct amdgpu_device *adev = hwmgr->adev; in vega12_hwmgr_backend_init()
380 hwmgr->backend = data; in vega12_hwmgr_backend_init()
382 vega12_set_default_registry_data(hwmgr); in vega12_hwmgr_backend_init()
395 vega12_set_features_platform_caps(hwmgr); in vega12_hwmgr_backend_init()
397 vega12_init_dpm_defaults(hwmgr); in vega12_hwmgr_backend_init()
400 vega12_set_private_data_based_on_pptable(hwmgr); in vega12_hwmgr_backend_init()
404 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = in vega12_hwmgr_backend_init()
406 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; in vega12_hwmgr_backend_init()
407 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; in vega12_hwmgr_backend_init()
409 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ in vega12_hwmgr_backend_init()
411 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
412 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in vega12_hwmgr_backend_init()
417 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; in vega12_hwmgr_backend_init()
419 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature; in vega12_hwmgr_backend_init()
421 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit; in vega12_hwmgr_backend_init()
423 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * in vega12_hwmgr_backend_init()
424 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; in vega12_hwmgr_backend_init()
426 if (hwmgr->feature_mask & PP_GFXOFF_MASK) in vega12_hwmgr_backend_init()
434 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) in vega12_init_sclk_threshold() argument
437 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_init_sclk_threshold()
444 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) in vega12_setup_asic_task() argument
446 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), in vega12_setup_asic_task()
468 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, in vega12_get_number_of_dpm_level() argument
473 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_get_number_of_dpm_level()
480 *num_of_levels = smum_get_argument(hwmgr); in vega12_get_number_of_dpm_level()
488 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, in vega12_get_dpm_frequency_by_index() argument
497 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_get_dpm_frequency_by_index()
502 *clock = smum_get_argument(hwmgr); in vega12_get_dpm_frequency_by_index()
507 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, in vega12_setup_single_dpm_table() argument
513 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); in vega12_setup_single_dpm_table()
521 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); in vega12_setup_single_dpm_table()
540 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) in vega12_setup_default_dpm_tables() argument
544 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_setup_default_dpm_tables()
553 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
566 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega12_setup_default_dpm_tables()
579 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); in vega12_setup_default_dpm_tables()
592 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); in vega12_setup_default_dpm_tables()
605 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); in vega12_setup_default_dpm_tables()
618 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); in vega12_setup_default_dpm_tables()
631 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); in vega12_setup_default_dpm_tables()
644 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); in vega12_setup_default_dpm_tables()
655 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); in vega12_setup_default_dpm_tables()
666 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); in vega12_setup_default_dpm_tables()
682 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
684 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
688 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
689 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
701 hwmgr->default_compute_power_profile.min_sclk =
704 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
705 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
718 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) in vega12_init_smc_table() argument
722 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_init_smc_table()
726 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_init_smc_table()
728 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); in vega12_init_smc_table()
741 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_init_smc_table()
748 result = vega12_copy_table_to_smc(hwmgr, in vega12_init_smc_table()
756 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) in vega12_set_allowed_featuresmask() argument
759 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_allowed_featuresmask()
770 …smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_… in vega12_set_allowed_featuresmask()
775 …smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_l… in vega12_set_allowed_featuresmask()
782 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) in vega12_init_powergate_state() argument
785 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_init_powergate_state()
797 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) in vega12_enable_all_smu_features() argument
800 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_enable_all_smu_features()
806 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures) == 0, in vega12_enable_all_smu_features()
810 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { in vega12_enable_all_smu_features()
818 vega12_init_powergate_state(hwmgr); in vega12_enable_all_smu_features()
823 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) in vega12_disable_all_smu_features() argument
826 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_disable_all_smu_features()
832 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures) == 0, in vega12_disable_all_smu_features()
836 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { in vega12_disable_all_smu_features()
848 struct pp_hwmgr *hwmgr) in vega12_odn_initialize_default_settings() argument
853 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, in vega12_set_overdrive_target_percentage() argument
856 return smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_set_overdrive_target_percentage()
860 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) in vega12_power_control_set_level() argument
866 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? in vega12_power_control_set_level()
867 hwmgr->platform_descriptor.TDPAdjustment : in vega12_power_control_set_level()
868 (-1 * hwmgr->platform_descriptor.TDPAdjustment); in vega12_power_control_set_level()
869 result = vega12_set_overdrive_target_percentage(hwmgr, in vega12_power_control_set_level()
875 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, in vega12_get_all_clock_ranges_helper() argument
880 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0, in vega12_get_all_clock_ranges_helper()
883 clock->ACMax = smum_get_argument(hwmgr); in vega12_get_all_clock_ranges_helper()
887 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0, in vega12_get_all_clock_ranges_helper()
890 clock->ACMin = smum_get_argument(hwmgr); in vega12_get_all_clock_ranges_helper()
894 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0, in vega12_get_all_clock_ranges_helper()
897 clock->DCMax = smum_get_argument(hwmgr); in vega12_get_all_clock_ranges_helper()
902 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) in vega12_get_all_clock_ranges() argument
905 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_all_clock_ranges()
909 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, in vega12_get_all_clock_ranges()
917 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) in vega12_enable_dpm_tasks() argument
921 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_enable_dpm_tasks()
924 result = vega12_set_allowed_featuresmask(hwmgr); in vega12_enable_dpm_tasks()
929 tmp_result = vega12_init_smc_table(hwmgr); in vega12_enable_dpm_tasks()
934 result = vega12_enable_all_smu_features(hwmgr); in vega12_enable_dpm_tasks()
939 tmp_result = vega12_power_control_set_level(hwmgr); in vega12_enable_dpm_tasks()
944 result = vega12_get_all_clock_ranges(hwmgr); in vega12_enable_dpm_tasks()
949 result = vega12_odn_initialize_default_settings(hwmgr); in vega12_enable_dpm_tasks()
954 result = vega12_setup_default_dpm_tables(hwmgr); in vega12_enable_dpm_tasks()
961 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, in vega12_patch_boot_state() argument
1006 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) in vega12_upload_dpm_min_level() argument
1008 struct vega12_hwmgr *data = hwmgr->backend; in vega12_upload_dpm_min_level()
1015 hwmgr, PPSMC_MSG_SetSoftMinByFreq, in vega12_upload_dpm_min_level()
1024 hwmgr, PPSMC_MSG_SetSoftMinByFreq, in vega12_upload_dpm_min_level()
1031 hwmgr, PPSMC_MSG_SetHardMinByFreq, in vega12_upload_dpm_min_level()
1041 hwmgr, PPSMC_MSG_SetSoftMinByFreq, in vega12_upload_dpm_min_level()
1049 hwmgr, PPSMC_MSG_SetSoftMinByFreq, in vega12_upload_dpm_min_level()
1059 hwmgr, PPSMC_MSG_SetSoftMinByFreq, in vega12_upload_dpm_min_level()
1069 hwmgr, PPSMC_MSG_SetSoftMinByFreq, in vega12_upload_dpm_min_level()
1079 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) in vega12_upload_dpm_max_level() argument
1081 struct vega12_hwmgr *data = hwmgr->backend; in vega12_upload_dpm_max_level()
1089 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, in vega12_upload_dpm_max_level()
1099 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, in vega12_upload_dpm_max_level()
1109 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, in vega12_upload_dpm_max_level()
1116 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, in vega12_upload_dpm_max_level()
1126 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, in vega12_upload_dpm_max_level()
1136 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, in vega12_upload_dpm_max_level()
1145 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) in vega12_enable_disable_vce_dpm() argument
1148 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_enable_disable_vce_dpm()
1151 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, in vega12_enable_disable_vce_dpm()
1162 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) in vega12_dpm_get_sclk() argument
1165 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_dpm_get_sclk()
1173 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0, in vega12_dpm_get_sclk()
1178 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0, in vega12_dpm_get_sclk()
1185 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) in vega12_dpm_get_mclk() argument
1188 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_dpm_get_mclk()
1196 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, in vega12_dpm_get_mclk()
1201 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, in vega12_dpm_get_mclk()
1208 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) in vega12_get_gpu_power() argument
1213 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, in vega12_get_gpu_power()
1218 value = smum_get_argument(hwmgr); in vega12_get_gpu_power()
1225 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) in vega12_get_current_gfx_clk_freq() argument
1231 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_get_current_gfx_clk_freq()
1235 gfx_clk = smum_get_argument(hwmgr); in vega12_get_current_gfx_clk_freq()
1242 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) in vega12_get_current_mclk_freq() argument
1249 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0, in vega12_get_current_mclk_freq()
1252 mem_clk = smum_get_argument(hwmgr); in vega12_get_current_mclk_freq()
1260 struct pp_hwmgr *hwmgr, in vega12_get_current_activity_percent() argument
1267 ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0); in vega12_get_current_activity_percent()
1269 current_activity = smum_get_argument(hwmgr); in vega12_get_current_activity_percent()
1284 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, in vega12_read_sensor() argument
1287 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_read_sensor()
1292 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); in vega12_read_sensor()
1297 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); in vega12_read_sensor()
1302 ret = vega12_get_current_activity_percent(hwmgr, (uint32_t *)value); in vega12_read_sensor()
1307 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); in vega12_read_sensor()
1319 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); in vega12_read_sensor()
1329 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, in vega12_notify_smc_display_change() argument
1332 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_notify_smc_display_change()
1335 return smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_notify_smc_display_change()
1342 int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, in vega12_display_clock_voltage_request() argument
1346 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_display_clock_voltage_request()
1374 result = smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_display_clock_voltage_request()
1384 struct pp_hwmgr *hwmgr) in vega12_notify_smc_display_config_after_ps_adjustment() argument
1387 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_notify_smc_display_config_after_ps_adjustment()
1391 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1392 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1393 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1394 vega12_notify_smc_display_change(hwmgr, false); in vega12_notify_smc_display_config_after_ps_adjustment()
1396 vega12_notify_smc_display_change(hwmgr, true); in vega12_notify_smc_display_config_after_ps_adjustment()
1398 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1399 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1400 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1405 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { in vega12_notify_smc_display_config_after_ps_adjustment()
1409 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, in vega12_notify_smc_display_config_after_ps_adjustment()
1421 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) in vega12_force_dpm_highest() argument
1424 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_force_dpm_highest()
1440 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), in vega12_force_dpm_highest()
1444 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), in vega12_force_dpm_highest()
1451 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) in vega12_force_dpm_lowest() argument
1454 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_force_dpm_lowest()
1469 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), in vega12_force_dpm_lowest()
1473 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), in vega12_force_dpm_lowest()
1481 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) in vega12_unforce_dpm_levels() argument
1483 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), in vega12_unforce_dpm_levels()
1487 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), in vega12_unforce_dpm_levels()
1494 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, in vega12_get_profiling_clk_mask() argument
1497 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_profiling_clk_mask()
1527 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) in vega12_set_fan_control_mode() argument
1534 vega12_fan_ctrl_stop_smc_fan_control(hwmgr); in vega12_set_fan_control_mode()
1538 vega12_fan_ctrl_start_smc_fan_control(hwmgr); in vega12_set_fan_control_mode()
1545 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, in vega12_dpm_force_dpm_level() argument
1555 ret = vega12_force_dpm_highest(hwmgr); in vega12_dpm_force_dpm_level()
1558 ret = vega12_force_dpm_lowest(hwmgr); in vega12_dpm_force_dpm_level()
1561 ret = vega12_unforce_dpm_levels(hwmgr); in vega12_dpm_force_dpm_level()
1567 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1570 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega12_dpm_force_dpm_level()
1571 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
1582 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) in vega12_get_fan_control_mode() argument
1584 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_fan_control_mode()
1592 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, in vega12_get_dal_power_level() argument
1597 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega12_get_dal_power_level()
1607 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, in vega12_get_clock_ranges() argument
1612 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_clock_ranges()
1622 static int vega12_get_sclks(struct pp_hwmgr *hwmgr, in vega12_get_sclks() argument
1625 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_sclks()
1649 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, in vega12_get_mem_latency() argument
1655 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, in vega12_get_memclocks() argument
1658 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_memclocks()
1674 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); in vega12_get_memclocks()
1682 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, in vega12_get_dcefclocks() argument
1685 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_dcefclocks()
1710 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, in vega12_get_socclocks() argument
1713 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_get_socclocks()
1739 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, in vega12_get_clock_by_type_with_latency() argument
1747 ret = vega12_get_sclks(hwmgr, clocks); in vega12_get_clock_by_type_with_latency()
1750 ret = vega12_get_memclocks(hwmgr, clocks); in vega12_get_clock_by_type_with_latency()
1753 ret = vega12_get_dcefclocks(hwmgr, clocks); in vega12_get_clock_by_type_with_latency()
1756 ret = vega12_get_socclocks(hwmgr, clocks); in vega12_get_clock_by_type_with_latency()
1765 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, in vega12_get_clock_by_type_with_voltage() argument
1774 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, in vega12_set_watermarks_for_clocks_ranges() argument
1777 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_watermarks_for_clocks_ranges()
1792 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, in vega12_force_clock_level() argument
1795 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_force_clock_level()
1809 ret = vega12_upload_dpm_min_level(hwmgr); in vega12_force_clock_level()
1814 ret = vega12_upload_dpm_max_level(hwmgr); in vega12_force_clock_level()
1829 ret = vega12_upload_dpm_min_level(hwmgr); in vega12_force_clock_level()
1834 ret = vega12_upload_dpm_max_level(hwmgr); in vega12_force_clock_level()
1851 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, in vega12_print_clock_levels() argument
1860 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0, in vega12_print_clock_levels()
1865 vega12_get_sclks(hwmgr, &clocks) == 0, in vega12_print_clock_levels()
1876 vega12_get_current_mclk_freq(hwmgr, &now) == 0, in vega12_print_clock_levels()
1881 vega12_get_memclocks(hwmgr, &clocks) == 0, in vega12_print_clock_levels()
1899 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) in vega12_apply_clocks_adjust_rules() argument
1901 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_apply_clocks_adjust_rules()
1907 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
1908 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
1910 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
1925 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega12_apply_clocks_adjust_rules()
1930 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
1949 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega12_apply_clocks_adjust_rules()
1954 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
1961 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()
1962 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega12_apply_clocks_adjust_rules()
1969 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega12_apply_clocks_adjust_rules()
1977 if (hwmgr->display_config->nb_pstate_switch_disable) in vega12_apply_clocks_adjust_rules()
1993 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2012 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2031 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2050 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2059 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, in vega12_set_uclk_to_highest_dpm_level() argument
2062 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_set_uclk_to_highest_dpm_level()
2074 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_set_uclk_to_highest_dpm_level()
2084 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) in vega12_pre_display_configuration_changed_task() argument
2086 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_pre_display_configuration_changed_task()
2089 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_pre_display_configuration_changed_task()
2092 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr, in vega12_pre_display_configuration_changed_task()
2098 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) in vega12_display_configuration_changed_task() argument
2100 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_display_configuration_changed_task()
2106 result = vega12_copy_table_to_smc(hwmgr, in vega12_display_configuration_changed_task()
2115 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_display_configuration_changed_task()
2116 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display); in vega12_display_configuration_changed_task()
2121 int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) in vega12_enable_disable_uvd_dpm() argument
2124 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_enable_disable_uvd_dpm()
2127 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, in vega12_enable_disable_uvd_dpm()
2138 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) in vega12_power_gate_vce() argument
2140 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_power_gate_vce()
2146 vega12_enable_disable_vce_dpm(hwmgr, !bgate); in vega12_power_gate_vce()
2149 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) in vega12_power_gate_uvd() argument
2151 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_power_gate_uvd()
2157 vega12_enable_disable_uvd_dpm(hwmgr, !bgate); in vega12_power_gate_uvd()
2161 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) in vega12_check_smc_update_required_for_display_configuration() argument
2163 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_check_smc_update_required_for_display_configuration()
2166 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega12_check_smc_update_required_for_display_configuration()
2170 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) in vega12_check_smc_update_required_for_display_configuration()
2177 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) in vega12_disable_dpm_tasks() argument
2181 tmp_result = vega12_disable_all_smu_features(hwmgr); in vega12_disable_dpm_tasks()
2188 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) in vega12_power_off_asic() argument
2190 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_power_off_asic()
2193 result = vega12_disable_dpm_tasks(hwmgr); in vega12_power_off_asic()
2203 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2207 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2230 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2236 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2238 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2252 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2257 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2259 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2276 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2282 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, in vega12_notify_cac_buffer_info() argument
2289 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_notify_cac_buffer_info()
2292 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_notify_cac_buffer_info()
2295 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_notify_cac_buffer_info()
2299 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_notify_cac_buffer_info()
2303 smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_notify_cac_buffer_info()
2309 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, in vega12_get_thermal_temperature_range() argument
2313 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_get_thermal_temperature_range()
2323 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) in vega12_enable_gfx_off() argument
2326 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_enable_gfx_off()
2330 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff); in vega12_enable_gfx_off()
2335 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) in vega12_disable_gfx_off() argument
2338 (struct vega12_hwmgr *)(hwmgr->backend); in vega12_disable_gfx_off()
2342 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff); in vega12_disable_gfx_off()
2347 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) in vega12_gfx_off_control() argument
2350 return vega12_enable_gfx_off(hwmgr); in vega12_gfx_off_control()
2352 return vega12_disable_gfx_off(hwmgr); in vega12_gfx_off_control()
2407 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) in vega12_hwmgr_init() argument
2409 hwmgr->hwmgr_func = &vega12_hwmgr_funcs; in vega12_hwmgr_init()
2410 hwmgr->pptable_func = &vega12_pptable_funcs; in vega12_hwmgr_init()