95 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)  in vega10_set_default_registry_data()  argument
97 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_default_registry_data()
100 			hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;  in vega10_set_default_registry_data()
102 			hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;  in vega10_set_default_registry_data()
104 			hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;  in vega10_set_default_registry_data()
106 			hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;  in vega10_set_default_registry_data()
109 			hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;  in vega10_set_default_registry_data()
111 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {  in vega10_set_default_registry_data()
118 			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;  in vega10_set_default_registry_data()
121 			hwmgr->feature_mask & PP_ULV_MASK ? true : false;  in vega10_set_default_registry_data()
124 			hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;  in vega10_set_default_registry_data()
172 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)  in vega10_set_features_platform_caps()  argument
174 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_features_platform_caps()
176 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_set_features_platform_caps()
177 	struct amdgpu_device *adev = hwmgr->adev;  in vega10_set_features_platform_caps()
179 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
182 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
186 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
189 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
193 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
197 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
200 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
203 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
206 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
209 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
212 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
217 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
219 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
221 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
223 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
225 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
227 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
229 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
231 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
233 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
235 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
239 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);  in vega10_set_features_platform_caps()
241 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);  in vega10_set_features_platform_caps()
243 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);  in vega10_set_features_platform_caps()
245 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);  in vega10_set_features_platform_caps()
247 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);  in vega10_set_features_platform_caps()
249 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);  in vega10_set_features_platform_caps()
251 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);  in vega10_set_features_platform_caps()
253 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);  in vega10_set_features_platform_caps()
255 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);  in vega10_set_features_platform_caps()
259 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
261 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
266 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
269 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
271 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
274 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
276 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in vega10_set_features_platform_caps()
282 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)  in vega10_odn_initial_default_setting()  argument
284 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_odn_initial_default_setting()
286 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_odn_initial_default_setting()
296 	result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);  in vega10_odn_initial_default_setting()
326 …od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]-…  in vega10_odn_initial_default_setting()
327 					hwmgr->platform_descriptor.overdriveLimit.memoryClock :  in vega10_odn_initial_default_setting()
336 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)  in vega10_init_dpm_defaults()  argument
338 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_init_dpm_defaults()
341 	struct amdgpu_device *adev = hwmgr->adev;  in vega10_init_dpm_defaults()
343 	vega10_initialize_power_tune_defaults(hwmgr);  in vega10_init_dpm_defaults()
467 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);  in vega10_init_dpm_defaults()
468 	hwmgr->smu_version = smum_get_argument(hwmgr);  in vega10_init_dpm_defaults()
470 	if ((hwmgr->smu_version & 0xff000000) == 0x5000000)  in vega10_init_dpm_defaults()
478 	if ((hwmgr->chip_id == 0x6862 ||  in vega10_init_dpm_defaults()
479 		hwmgr->chip_id == 0x6861 ||  in vega10_init_dpm_defaults()
480 		hwmgr->chip_id == 0x6868) &&  in vega10_init_dpm_defaults()
487 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,  in vega10_get_socclk_for_voltage_evv()  argument
494 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_socclk_for_voltage_evv()
523 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)  in vega10_get_evv_voltages()  argument
525 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_get_evv_voltages()
531 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_evv_voltages()
539 		if (!vega10_get_socclk_for_voltage_evv(hwmgr,  in vega10_get_evv_voltages()
551 			PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,  in vega10_get_evv_voltages()
580 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,  in vega10_patch_with_vdd_leakage()  argument
607 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,  in vega10_patch_lookup_table_with_leakage()  argument
614 		vega10_patch_with_vdd_leakage(hwmgr,  in vega10_patch_lookup_table_with_leakage()
621 		struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,  in vega10_patch_clock_voltage_limits_with_vddc_leakage()  argument
624 	vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);  in vega10_patch_clock_voltage_limits_with_vddc_leakage()
631 		struct pp_hwmgr *hwmgr)  in vega10_patch_voltage_dependency_tables_with_lookup_table()  argument
636 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_patch_voltage_dependency_tables_with_lookup_table()
683 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,  in vega10_sort_lookup_table()  argument
709 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)  in vega10_complete_dependency_tables()  argument
714 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_complete_dependency_tables()
716 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_complete_dependency_tables()
718 	tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,  in vega10_complete_dependency_tables()
723 	tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,  in vega10_complete_dependency_tables()
729 	tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);  in vega10_complete_dependency_tables()
733 	tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);  in vega10_complete_dependency_tables()
740 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)  in vega10_set_private_data_based_on_pptable()  argument
743 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_set_private_data_based_on_pptable()
768 	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =  in vega10_set_private_data_based_on_pptable()
770 	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =  in vega10_set_private_data_based_on_pptable()
772 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =  in vega10_set_private_data_based_on_pptable()
774 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =  in vega10_set_private_data_based_on_pptable()
780 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)  in vega10_hwmgr_backend_fini()  argument
782 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);  in vega10_hwmgr_backend_fini()
783 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;  in vega10_hwmgr_backend_fini()
785 	kfree(hwmgr->backend);  in vega10_hwmgr_backend_fini()
786 	hwmgr->backend = NULL;  in vega10_hwmgr_backend_fini()
791 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)  in vega10_hwmgr_backend_init()  argument
797 	struct amdgpu_device *adev = hwmgr->adev;  in vega10_hwmgr_backend_init()
803 	hwmgr->backend = data;  in vega10_hwmgr_backend_init()
805 	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];  in vega10_hwmgr_backend_init()
806 	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;  in vega10_hwmgr_backend_init()
807 	hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;  in vega10_hwmgr_backend_init()
809 	vega10_set_default_registry_data(hwmgr);  in vega10_hwmgr_backend_init()
818 	if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,  in vega10_hwmgr_backend_init()
820 		if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,  in vega10_hwmgr_backend_init()
828 		kfree(hwmgr->backend);  in vega10_hwmgr_backend_init()
829 		hwmgr->backend = NULL;  in vega10_hwmgr_backend_init()
836 	if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,  in vega10_hwmgr_backend_init()
838 		if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,  in vega10_hwmgr_backend_init()
850 		if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,  in vega10_hwmgr_backend_init()
857 	vega10_set_features_platform_caps(hwmgr);  in vega10_hwmgr_backend_init()
859 	vega10_init_dpm_defaults(hwmgr);  in vega10_hwmgr_backend_init()
863 	PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),  in vega10_hwmgr_backend_init()
871 	vega10_complete_dependency_tables(hwmgr);  in vega10_hwmgr_backend_init()
874 	vega10_set_private_data_based_on_pptable(hwmgr);  in vega10_hwmgr_backend_init()
878 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  in vega10_hwmgr_backend_init()
880 	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;  in vega10_hwmgr_backend_init()
881 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;  in vega10_hwmgr_backend_init()
883 	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */  in vega10_hwmgr_backend_init()
885 	hwmgr->platform_descriptor.clockStep.engineClock = 500;  in vega10_hwmgr_backend_init()
886 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;  in vega10_hwmgr_backend_init()
891 			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;  in vega10_hwmgr_backend_init()
893 			hwmgr->thermal_controller.  in vega10_hwmgr_backend_init()
896 			hwmgr->thermal_controller.advanceFanControlParameters.  in vega10_hwmgr_backend_init()
899 			hwmgr->thermal_controller.  in vega10_hwmgr_backend_init()
901 			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;  in vega10_hwmgr_backend_init()
913 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)  in vega10_init_sclk_threshold()  argument
915 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_init_sclk_threshold()
922 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)  in vega10_setup_dpm_led_config()  argument
924 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_setup_dpm_led_config()
933 	ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,  in vega10_setup_dpm_led_config()
954 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)  in vega10_setup_asic_task()  argument
956 	PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),  in vega10_setup_asic_task()
960 	PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),  in vega10_setup_asic_task()
964 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);  in vega10_setup_asic_task()
977 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,  in vega10_trim_voltage_table()  argument
1021 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,  in vega10_get_mvdd_voltage_table()  argument
1040 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,  in vega10_get_mvdd_voltage_table()
1048 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,  in vega10_get_vddci_voltage_table()  argument
1067 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),  in vega10_get_vddci_voltage_table()
1074 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,  in vega10_get_vdd_voltage_table()  argument
1102 		struct pp_hwmgr *hwmgr,  in vega10_trim_voltage_table_to_fit_state_table()  argument
1125 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)  in vega10_construct_voltage_tables()  argument
1127 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_construct_voltage_tables()
1129 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_construct_voltage_tables()
1134 		result = vega10_get_mvdd_voltage_table(hwmgr,  in vega10_construct_voltage_tables()
1143 		result = vega10_get_vddci_voltage_table(hwmgr,  in vega10_construct_voltage_tables()
1153 		result = vega10_get_vdd_voltage_table(hwmgr,  in vega10_construct_voltage_tables()
1163 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,  in vega10_construct_voltage_tables()
1168 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,  in vega10_construct_voltage_tables()
1173 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,  in vega10_construct_voltage_tables()
1195 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,  in vega10_setup_default_single_dpm_table()  argument
1213 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)  in vega10_setup_default_pcie_table()  argument
1215 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_setup_default_pcie_table()
1218 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_setup_default_pcie_table()
1262 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)  in vega10_setup_default_dpm_tables()  argument
1264 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_setup_default_dpm_tables()
1266 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_setup_default_dpm_tables()
1310 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1317 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1320 	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)  in vega10_setup_default_dpm_tables()
1321 		hwmgr->platform_descriptor.overdriveLimit.engineClock =  in vega10_setup_default_dpm_tables()
1328 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1331 	if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)  in vega10_setup_default_dpm_tables()
1332 		hwmgr->platform_descriptor.overdriveLimit.memoryClock =  in vega10_setup_default_dpm_tables()
1384 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1391 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1398 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1405 	vega10_setup_default_single_dpm_table(hwmgr,  in vega10_setup_default_dpm_tables()
1411 	vega10_setup_default_pcie_table(hwmgr);  in vega10_setup_default_dpm_tables()
1427 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)  in vega10_populate_ulv_state()  argument
1429 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_ulv_state()
1431 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_ulv_state()
1450 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_lclk_level()  argument
1456 			hwmgr,  in vega10_populate_single_lclk_level()
1467 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_smc_link_levels()  argument
1470 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_smc_link_levels()
1480 		result = vega10_populate_single_lclk_level(hwmgr,  in vega10_populate_smc_link_levels()
1493 		result = vega10_populate_single_lclk_level(hwmgr,  in vega10_populate_smc_link_levels()
1513 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_gfx_level()  argument
1518 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_gfx_level()
1520 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_single_gfx_level()
1523 			hwmgr->platform_descriptor.overdriveLimit.engineClock;  in vega10_populate_single_gfx_level()
1526 	if (hwmgr->od_enabled)  in vega10_populate_single_gfx_level()
1548 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,  in vega10_populate_single_gfx_level()
1578 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_soc_level()  argument
1582 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_single_soc_level()
1584 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_soc_level()
1589 	if (hwmgr->od_enabled) {  in vega10_populate_single_soc_level()
1608 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,  in vega10_populate_single_soc_level()
1624 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_all_graphic_levels()  argument
1626 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_all_graphic_levels()
1628 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_all_graphic_levels()
1635 		result = vega10_populate_single_gfx_level(hwmgr,  in vega10_populate_all_graphic_levels()
1645 		result = vega10_populate_single_gfx_level(hwmgr,  in vega10_populate_all_graphic_levels()
1659 		result = vega10_populate_single_soc_level(hwmgr,  in vega10_populate_all_graphic_levels()
1669 		result = vega10_populate_single_soc_level(hwmgr,  in vega10_populate_all_graphic_levels()
1681 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_vddc_soc_levels()  argument
1683 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_vddc_soc_levels()
1685 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;  in vega10_populate_vddc_soc_levels()
1691 	if (hwmgr->od_enabled)  in vega10_populate_vddc_soc_levels()
1714 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_memory_level()  argument
1718 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_single_memory_level()
1720 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_memory_level()
1724 			hwmgr->platform_descriptor.overdriveLimit.memoryClock;  in vega10_populate_single_memory_level()
1727 	if (hwmgr->od_enabled)  in vega10_populate_single_memory_level()
1750 			hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),  in vega10_populate_single_memory_level()
1774 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_all_memory_levels()  argument
1776 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_all_memory_levels()
1784 		result = vega10_populate_single_memory_level(hwmgr,  in vega10_populate_all_memory_levels()
1795 		result = vega10_populate_single_memory_level(hwmgr,  in vega10_populate_all_memory_levels()
1816 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,  in vega10_populate_single_display_type()  argument
1819 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_single_display_type()
1823 			(hwmgr->pptable);  in vega10_populate_single_display_type()
1872 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_all_display_clock_levels()  argument
1877 		PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),  in vega10_populate_all_display_clock_levels()
1885 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_eclock_level()  argument
1890 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_single_eclock_level()
1896 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,  in vega10_populate_single_eclock_level()
1912 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_smc_vce_levels()  argument
1914 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_smc_vce_levels()
1921 		result = vega10_populate_single_eclock_level(hwmgr,  in vega10_populate_smc_vce_levels()
1931 		result = vega10_populate_single_eclock_level(hwmgr,  in vega10_populate_smc_vce_levels()
1943 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_vclock_level()  argument
1948 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,  in vega10_populate_single_vclock_level()
1959 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,  in vega10_populate_single_dclock_level()  argument
1964 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,  in vega10_populate_single_dclock_level()
1975 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)  in vega10_populate_smc_uvd_levels()  argument
1977 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_smc_uvd_levels()
1984 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_smc_uvd_levels()
1991 		result = vega10_populate_single_vclock_level(hwmgr,  in vega10_populate_smc_uvd_levels()
2000 		result = vega10_populate_single_vclock_level(hwmgr,  in vega10_populate_smc_uvd_levels()
2009 		result = vega10_populate_single_dclock_level(hwmgr,  in vega10_populate_smc_uvd_levels()
2018 		result = vega10_populate_single_dclock_level(hwmgr,  in vega10_populate_smc_uvd_levels()
2046 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)  in vega10_populate_clock_stretcher_table()  argument
2048 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_clock_stretcher_table()
2051 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_clock_stretcher_table()
2065 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)  in vega10_populate_avfs_parameters()  argument
2067 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_avfs_parameters()
2070 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_populate_avfs_parameters()
2081 		result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);  in vega10_populate_avfs_parameters()
2256 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)  in vega10_acg_enable()  argument
2258 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_acg_enable()
2262 		if (0 == vega10_enable_smc_features(hwmgr, true,  in vega10_acg_enable()
2266 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);  in vega10_acg_enable()
2268 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);  in vega10_acg_enable()
2269 		agc_btc_response = smum_get_argument(hwmgr);  in vega10_acg_enable()
2273 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);  in vega10_acg_enable()
2275 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);  in vega10_acg_enable()
2276 			if (0 == vega10_enable_smc_features(hwmgr, true,  in vega10_acg_enable()
2288 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)  in vega10_acg_disable()  argument
2290 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_acg_disable()
2294 		if (!vega10_enable_smc_features(hwmgr, false,  in vega10_acg_disable()
2301 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)  in vega10_populate_gpio_parameters()  argument
2303 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_gpio_parameters()
2308 	result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);  in vega10_populate_gpio_parameters()
2336 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)  in vega10_avfs_enable()  argument
2338 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_avfs_enable()
2342 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_avfs_enable()
2349 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_avfs_enable()
2361 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)  in vega10_update_avfs()  argument
2363 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_update_avfs()
2366 		vega10_avfs_enable(hwmgr, false);  in vega10_update_avfs()
2368 		vega10_avfs_enable(hwmgr, false);  in vega10_update_avfs()
2369 		vega10_avfs_enable(hwmgr, true);  in vega10_update_avfs()
2371 		vega10_avfs_enable(hwmgr, true);  in vega10_update_avfs()
2377 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)  in vega10_populate_and_upload_avfs_fuse_override()  argument
2385 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_and_upload_avfs_fuse_override()
2388 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);  in vega10_populate_and_upload_avfs_fuse_override()
2389 	top32 = smum_get_argument(hwmgr);  in vega10_populate_and_upload_avfs_fuse_override()
2391 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);  in vega10_populate_and_upload_avfs_fuse_override()
2392 	bottom32 = smum_get_argument(hwmgr);  in vega10_populate_and_upload_avfs_fuse_override()
2406 		result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,  in vega10_populate_and_upload_avfs_fuse_override()
2416 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)  in vega10_check_dpm_table_updated()  argument
2418 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_check_dpm_table_updated()
2420 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;  in vega10_check_dpm_table_updated()
2457 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)  in vega10_init_smc_table()  argument
2460 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_init_smc_table()
2462 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_init_smc_table()
2468 	result = vega10_setup_default_dpm_tables(hwmgr);  in vega10_init_smc_table()
2474 	if (hwmgr->od_enabled) {  in vega10_init_smc_table()
2477 			vega10_check_dpm_table_updated(hwmgr);  in vega10_init_smc_table()
2479 			vega10_odn_initial_default_setting(hwmgr);  in vega10_init_smc_table()
2483 	pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,  in vega10_init_smc_table()
2508 		result = vega10_populate_ulv_state(hwmgr);  in vega10_init_smc_table()
2514 	result = vega10_populate_smc_link_levels(hwmgr);  in vega10_init_smc_table()
2519 	result = vega10_populate_all_graphic_levels(hwmgr);  in vega10_init_smc_table()
2524 	result = vega10_populate_all_memory_levels(hwmgr);  in vega10_init_smc_table()
2529 	vega10_populate_vddc_soc_levels(hwmgr);  in vega10_init_smc_table()
2531 	result = vega10_populate_all_display_clock_levels(hwmgr);  in vega10_init_smc_table()
2536 	result = vega10_populate_smc_vce_levels(hwmgr);  in vega10_init_smc_table()
2541 	result = vega10_populate_smc_uvd_levels(hwmgr);  in vega10_init_smc_table()
2547 		result = vega10_populate_clock_stretcher_table(hwmgr);  in vega10_init_smc_table()
2553 	result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);  in vega10_init_smc_table()
2560 		pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,  in vega10_init_smc_table()
2563 		pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,  in vega10_init_smc_table()
2569 			smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_init_smc_table()
2576 		smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_init_smc_table()
2581 	result = vega10_populate_avfs_parameters(hwmgr);  in vega10_init_smc_table()
2586 	result = vega10_populate_gpio_parameters(hwmgr);  in vega10_init_smc_table()
2600 	vega10_populate_and_upload_avfs_fuse_override(hwmgr);  in vega10_init_smc_table()
2602 	result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);  in vega10_init_smc_table()
2607 	result = vega10_avfs_enable(hwmgr, true);  in vega10_init_smc_table()
2610 	vega10_acg_enable(hwmgr);  in vega10_init_smc_table()
2615 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)  in vega10_enable_thermal_protection()  argument
2617 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_thermal_protection()
2624 				!vega10_enable_smc_features(hwmgr,  in vega10_enable_thermal_protection()
2635 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)  in vega10_disable_thermal_protection()  argument
2637 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_disable_thermal_protection()
2644 				!vega10_enable_smc_features(hwmgr,  in vega10_disable_thermal_protection()
2655 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)  in vega10_enable_vrhot_feature()  argument
2657 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_vrhot_feature()
2662 					!vega10_enable_smc_features(hwmgr,  in vega10_enable_vrhot_feature()
2671 						!vega10_enable_smc_features(hwmgr,  in vega10_enable_vrhot_feature()
2683 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)  in vega10_enable_ulv()  argument
2685 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_ulv()
2688 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_ulv()
2698 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)  in vega10_disable_ulv()  argument
2700 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_disable_ulv()
2703 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_disable_ulv()
2713 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)  in vega10_enable_deep_sleep_master_switch()  argument
2715 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_deep_sleep_master_switch()
2718 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_deep_sleep_master_switch()
2726 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_deep_sleep_master_switch()
2734 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_deep_sleep_master_switch()
2742 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_deep_sleep_master_switch()
2752 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)  in vega10_disable_deep_sleep_master_switch()  argument
2754 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_disable_deep_sleep_master_switch()
2757 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_disable_deep_sleep_master_switch()
2765 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_disable_deep_sleep_master_switch()
2773 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_disable_deep_sleep_master_switch()
2781 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_disable_deep_sleep_master_switch()
2791 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)  in vega10_stop_dpm()  argument
2793 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_stop_dpm()
2798 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_stop_dpm()
2816 	vega10_enable_smc_features(hwmgr, false, feature_mask);  in vega10_stop_dpm()
2828 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)  in vega10_start_dpm()  argument
2830 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_start_dpm()
2845 	if (vega10_enable_smc_features(hwmgr,  in vega10_start_dpm()
2855 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_start_dpm()
2862 		smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_start_dpm()
2869 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_start_dpm()
2880 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)  in vega10_enable_disable_PCC_limit_feature()  argument
2882 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_disable_PCC_limit_feature()
2887 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_disable_PCC_limit_feature()
2897 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)  in vega10_enable_dpm_tasks()  argument
2899 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_dpm_tasks()
2902 	vega10_enable_disable_PCC_limit_feature(hwmgr, true);  in vega10_enable_dpm_tasks()
2904 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_enable_dpm_tasks()
2907 	tmp_result = vega10_construct_voltage_tables(hwmgr);  in vega10_enable_dpm_tasks()
2912 	tmp_result = vega10_init_smc_table(hwmgr);  in vega10_enable_dpm_tasks()
2918 		tmp_result = vega10_enable_thermal_protection(hwmgr);  in vega10_enable_dpm_tasks()
2924 	tmp_result = vega10_enable_vrhot_feature(hwmgr);  in vega10_enable_dpm_tasks()
2929 	tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);  in vega10_enable_dpm_tasks()
2934 	tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);  in vega10_enable_dpm_tasks()
2939 	tmp_result = vega10_enable_didt_config(hwmgr);  in vega10_enable_dpm_tasks()
2943 	tmp_result = vega10_enable_power_containment(hwmgr);  in vega10_enable_dpm_tasks()
2948 	tmp_result = vega10_power_control_set_level(hwmgr);  in vega10_enable_dpm_tasks()
2953 	tmp_result = vega10_enable_ulv(hwmgr);  in vega10_enable_dpm_tasks()
2961 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)  in vega10_get_power_state_size()  argument
2966 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,  in vega10_get_pp_table_entry_callback_func()  argument
3032 					hwmgr->platform_descriptor.  in vega10_get_pp_table_entry_callback_func()
3062 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,  in vega10_get_pp_table_entry()  argument
3072 	result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,  in vega10_get_pp_table_entry()
3089 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,  in vega10_patch_boot_state()  argument
3095 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,  in vega10_apply_state_adjust_rules()  argument
3099 	struct amdgpu_device *adev = hwmgr->adev;  in vega10_apply_state_adjust_rules()
3111 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_apply_state_adjust_rules()
3113 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_apply_state_adjust_rules()
3126 			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :  in vega10_apply_state_adjust_rules()
3127 			&(hwmgr->dyn_state.max_clock_voltage_on_dc);  in vega10_apply_state_adjust_rules()
3144 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;  in vega10_apply_state_adjust_rules()
3145 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;  in vega10_apply_state_adjust_rules()
3156 		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);  in vega10_apply_state_adjust_rules()
3185 	if (hwmgr->display_config->num_display == 0)  in vega10_apply_state_adjust_rules()
3188 		disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||  in vega10_apply_state_adjust_rules()
3220 		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;  in vega10_apply_state_adjust_rules()
3247 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)  in vega10_find_dpm_states_clocks_in_dpm_table()  argument
3249 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_find_dpm_states_clocks_in_dpm_table()
3251 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)  in vega10_find_dpm_states_clocks_in_dpm_table()
3258 		struct pp_hwmgr *hwmgr, const void *input)  in vega10_populate_and_upload_sclk_mclk_dpm_levels()  argument
3261 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3270 	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {  in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3276 	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {  in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3283 		result = vega10_populate_all_graphic_levels(hwmgr);  in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3291 		result = vega10_populate_all_memory_levels(hwmgr);  in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3297 	vega10_populate_vddc_soc_levels(hwmgr);  in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3302 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,  in vega10_trim_single_dpm_states()  argument
3318 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,  in vega10_trim_single_dpm_states_with_mask()  argument
3337 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,  in vega10_trim_dpm_states()  argument
3340 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_trim_dpm_states()
3349 	vega10_trim_single_dpm_states(hwmgr,  in vega10_trim_dpm_states()
3354 	vega10_trim_single_dpm_states_with_mask(hwmgr,  in vega10_trim_dpm_states()
3360 	vega10_trim_single_dpm_states(hwmgr,  in vega10_trim_dpm_states()
3400 		struct pp_hwmgr *hwmgr)  in vega10_apply_dal_minimum_voltage_request()  argument
3405 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)  in vega10_get_soc_index_for_max_uclk()  argument
3409 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_soc_index_for_max_uclk()
3416 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)  in vega10_upload_dpm_bootup_level()  argument
3418 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_upload_dpm_bootup_level()
3421 	vega10_apply_dal_minimum_voltage_request(hwmgr);  in vega10_upload_dpm_bootup_level()
3426 			smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_upload_dpm_bootup_level()
3438 				socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);  in vega10_upload_dpm_bootup_level()
3439 				smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_upload_dpm_bootup_level()
3443 				smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_upload_dpm_bootup_level()
3455 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)  in vega10_upload_dpm_max_level()  argument
3457 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_upload_dpm_max_level()
3459 	vega10_apply_dal_minimum_voltage_request(hwmgr);  in vega10_upload_dpm_max_level()
3464 			smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_upload_dpm_max_level()
3475 			smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_upload_dpm_max_level()
3487 		struct pp_hwmgr *hwmgr, const void *input)  in vega10_generate_dpm_level_enable_mask()  argument
3489 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_generate_dpm_level_enable_mask()
3496 	PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),  in vega10_generate_dpm_level_enable_mask()
3509 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),  in vega10_generate_dpm_level_enable_mask()
3512 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),  in vega10_generate_dpm_level_enable_mask()
3525 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)  in vega10_enable_disable_vce_dpm()  argument
3527 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_disable_vce_dpm()
3530 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_disable_vce_dpm()
3541 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)  in vega10_update_sclk_threshold()  argument
3543 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_update_sclk_threshold()
3555 		smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_update_sclk_threshold()
3563 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,  in vega10_set_power_state_tasks()  argument
3567 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_power_state_tasks()
3570 	tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);  in vega10_set_power_state_tasks()
3575 	tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);  in vega10_set_power_state_tasks()
3580 	tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);  in vega10_set_power_state_tasks()
3585 	tmp_result = vega10_update_sclk_threshold(hwmgr);  in vega10_set_power_state_tasks()
3590 	result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);  in vega10_set_power_state_tasks()
3594 	vega10_update_avfs(hwmgr);  in vega10_set_power_state_tasks()
3601 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)  in vega10_dpm_get_sclk()  argument
3606 	if (hwmgr == NULL)  in vega10_dpm_get_sclk()
3609 	ps = hwmgr->request_ps;  in vega10_dpm_get_sclk()
3623 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)  in vega10_dpm_get_mclk()  argument
3628 	if (hwmgr == NULL)  in vega10_dpm_get_mclk()
3631 	ps = hwmgr->request_ps;  in vega10_dpm_get_mclk()
3645 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,  in vega10_get_gpu_power()  argument
3653 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);  in vega10_get_gpu_power()
3654 	value = smum_get_argument(hwmgr);  in vega10_get_gpu_power()
3662 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,  in vega10_read_sensor()  argument
3665 	struct amdgpu_device *adev = hwmgr->adev;  in vega10_read_sensor()
3667 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_read_sensor()
3674 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);  in vega10_read_sensor()
3675 		sclk_mhz = smum_get_argument(hwmgr);  in vega10_read_sensor()
3679 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);  in vega10_read_sensor()
3680 		mclk_idx = smum_get_argument(hwmgr);  in vega10_read_sensor()
3689 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);  in vega10_read_sensor()
3690 		activity_percent = smum_get_argument(hwmgr);  in vega10_read_sensor()
3695 		*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);  in vega10_read_sensor()
3707 		ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);  in vega10_read_sensor()
3723 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,  in vega10_notify_smc_display_change()  argument
3726 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_notify_smc_display_change()
3731 int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,  in vega10_display_clock_voltage_request()  argument
3761 		smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_display_clock_voltage_request()
3769 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,  in vega10_get_uclk_index()  argument
3790 		struct pp_hwmgr *hwmgr)  in vega10_notify_smc_display_config_after_ps_adjustment()  argument
3792 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_notify_smc_display_config_after_ps_adjustment()
3796 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_notify_smc_display_config_after_ps_adjustment()
3803 	if ((hwmgr->display_config->num_display > 1) &&  in vega10_notify_smc_display_config_after_ps_adjustment()
3804 	     !hwmgr->display_config->multi_monitor_in_sync &&  in vega10_notify_smc_display_config_after_ps_adjustment()
3805 	     !hwmgr->display_config->nb_pstate_switch_disable)  in vega10_notify_smc_display_config_after_ps_adjustment()
3806 		vega10_notify_smc_display_change(hwmgr, false);  in vega10_notify_smc_display_config_after_ps_adjustment()
3808 		vega10_notify_smc_display_change(hwmgr, true);  in vega10_notify_smc_display_config_after_ps_adjustment()
3810 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;  in vega10_notify_smc_display_config_after_ps_adjustment()
3811 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;  in vega10_notify_smc_display_config_after_ps_adjustment()
3812 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;  in vega10_notify_smc_display_config_after_ps_adjustment()
3822 		if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {  in vega10_notify_smc_display_config_after_ps_adjustment()
3824 					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,  in vega10_notify_smc_display_config_after_ps_adjustment()
3834 		idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);  in vega10_notify_smc_display_config_after_ps_adjustment()
3835 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);  in vega10_notify_smc_display_config_after_ps_adjustment()
3842 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)  in vega10_force_dpm_highest()  argument
3844 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_force_dpm_highest()
3853 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),  in vega10_force_dpm_highest()
3857 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),  in vega10_force_dpm_highest()
3864 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)  in vega10_force_dpm_lowest()  argument
3866 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_force_dpm_lowest()
3875 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),  in vega10_force_dpm_lowest()
3879 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),  in vega10_force_dpm_lowest()
3887 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)  in vega10_unforce_dpm_levels()  argument
3889 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_unforce_dpm_levels()
3900 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),  in vega10_unforce_dpm_levels()
3904 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),  in vega10_unforce_dpm_levels()
3910 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,  in vega10_get_profiling_clk_mask()  argument
3914 			(struct phm_ppt_v2_information *)(hwmgr->pptable);  in vega10_get_profiling_clk_mask()
3922 		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;  in vega10_get_profiling_clk_mask()
3923 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;  in vega10_get_profiling_clk_mask()
3938 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)  in vega10_set_fan_control_mode()  argument
3942 		vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);  in vega10_set_fan_control_mode()
3946 			vega10_fan_ctrl_stop_smc_fan_control(hwmgr);  in vega10_set_fan_control_mode()
3950 			vega10_fan_ctrl_start_smc_fan_control(hwmgr);  in vega10_set_fan_control_mode()
3957 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,  in vega10_force_clock_level()  argument
3960 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_force_clock_level()
3967 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),  in vega10_force_clock_level()
3971 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),  in vega10_force_clock_level()
3980 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),  in vega10_force_clock_level()
3984 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),  in vega10_force_clock_level()
3998 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,  in vega10_dpm_force_dpm_level()  argument
4006 	if (hwmgr->pstate_sclk == 0)  in vega10_dpm_force_dpm_level()
4007 		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);  in vega10_dpm_force_dpm_level()
4011 		ret = vega10_force_dpm_highest(hwmgr);  in vega10_dpm_force_dpm_level()
4014 		ret = vega10_force_dpm_lowest(hwmgr);  in vega10_dpm_force_dpm_level()
4017 		ret = vega10_unforce_dpm_levels(hwmgr);  in vega10_dpm_force_dpm_level()
4023 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);  in vega10_dpm_force_dpm_level()
4026 		vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);  in vega10_dpm_force_dpm_level()
4027 		vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);  in vega10_dpm_force_dpm_level()
4036 …if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE…  in vega10_dpm_force_dpm_level()
4037 			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);  in vega10_dpm_force_dpm_level()
4038 …else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PR…  in vega10_dpm_force_dpm_level()
4039 			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);  in vega10_dpm_force_dpm_level()
4045 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)  in vega10_get_fan_control_mode()  argument
4047 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_get_fan_control_mode()
4055 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,  in vega10_get_dal_power_level()  argument
4059 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_dal_power_level()
4069 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,  in vega10_get_sclks()  argument
4073 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_sclks()
4089 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,  in vega10_get_memclocks()  argument
4093 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_memclocks()
4096 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_get_memclocks()
4115 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,  in vega10_get_dcefclocks()  argument
4119 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_dcefclocks()
4131 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,  in vega10_get_socclocks()  argument
4135 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_socclocks()
4147 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,  in vega10_get_clock_by_type_with_latency()  argument
4153 		vega10_get_sclks(hwmgr, clocks);  in vega10_get_clock_by_type_with_latency()
4156 		vega10_get_memclocks(hwmgr, clocks);  in vega10_get_clock_by_type_with_latency()
4159 		vega10_get_dcefclocks(hwmgr, clocks);  in vega10_get_clock_by_type_with_latency()
4162 		vega10_get_socclocks(hwmgr, clocks);  in vega10_get_clock_by_type_with_latency()
4171 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,  in vega10_get_clock_by_type_with_voltage()  argument
4176 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_clock_by_type_with_voltage()
4213 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,  in vega10_set_watermarks_for_clocks_ranges()  argument
4216 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_watermarks_for_clocks_ranges()
4229 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,  in vega10_print_clock_levels()  argument
4232 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_print_clock_levels()
4245 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);  in vega10_print_clock_levels()
4246 		now = smum_get_argument(hwmgr);  in vega10_print_clock_levels()
4257 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);  in vega10_print_clock_levels()
4258 		now = smum_get_argument(hwmgr);  in vega10_print_clock_levels()
4266 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);  in vega10_print_clock_levels()
4267 		now = smum_get_argument(hwmgr);  in vega10_print_clock_levels()
4277 		if (hwmgr->od_enabled) {  in vega10_print_clock_levels()
4287 		if (hwmgr->od_enabled) {  in vega10_print_clock_levels()
4297 		if (hwmgr->od_enabled) {  in vega10_print_clock_levels()
4301 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);  in vega10_print_clock_levels()
4304 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);  in vega10_print_clock_levels()
4316 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)  in vega10_display_configuration_changed_task()  argument
4318 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_display_configuration_changed_task()
4324 		result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);  in vega10_display_configuration_changed_task()
4330 		smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_display_configuration_changed_task()
4331 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);  in vega10_display_configuration_changed_task()
4337 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)  in vega10_enable_disable_uvd_dpm()  argument
4339 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_enable_disable_uvd_dpm()
4342 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,  in vega10_enable_disable_uvd_dpm()
4352 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)  in vega10_power_gate_vce()  argument
4354 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_power_gate_vce()
4357 	vega10_enable_disable_vce_dpm(hwmgr, !bgate);  in vega10_power_gate_vce()
4360 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)  in vega10_power_gate_uvd()  argument
4362 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_power_gate_uvd()
4365 	vega10_enable_disable_uvd_dpm(hwmgr, !bgate);  in vega10_power_gate_uvd()
4377 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,  in vega10_check_states_equal()  argument
4413 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)  in vega10_check_smc_update_required_for_display_configuration()  argument
4415 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_check_smc_update_required_for_display_configuration()
4418 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)  in vega10_check_smc_update_required_for_display_configuration()
4422 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)  in vega10_check_smc_update_required_for_display_configuration()
4429 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)  in vega10_disable_dpm_tasks()  argument
4434 		vega10_disable_thermal_protection(hwmgr);  in vega10_disable_dpm_tasks()
4436 	tmp_result = vega10_disable_power_containment(hwmgr);  in vega10_disable_dpm_tasks()
4440 	tmp_result = vega10_disable_didt_config(hwmgr);  in vega10_disable_dpm_tasks()
4444 	tmp_result = vega10_avfs_enable(hwmgr, false);  in vega10_disable_dpm_tasks()
4448 	tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);  in vega10_disable_dpm_tasks()
4452 	tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);  in vega10_disable_dpm_tasks()
4456 	tmp_result = vega10_disable_ulv(hwmgr);  in vega10_disable_dpm_tasks()
4460 	tmp_result =  vega10_acg_disable(hwmgr);  in vega10_disable_dpm_tasks()
4464 	vega10_enable_disable_PCC_limit_feature(hwmgr, false);  in vega10_disable_dpm_tasks()
4468 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)  in vega10_power_off_asic()  argument
4470 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_power_off_asic()
4473 	result = vega10_disable_dpm_tasks(hwmgr);  in vega10_power_off_asic()
4482 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)  in vega10_get_sclk_od()  argument
4484 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_get_sclk_od()
4500 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)  in vega10_set_sclk_od()  argument
4502 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_sclk_od()
4508 	ps = hwmgr->request_ps;  in vega10_set_sclk_od()
4525 			hwmgr->platform_descriptor.overdriveLimit.engineClock)  in vega10_set_sclk_od()
4528 				hwmgr->platform_descriptor.overdriveLimit.engineClock;  in vega10_set_sclk_od()
4533 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)  in vega10_get_mclk_od()  argument
4535 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_get_mclk_od()
4552 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)  in vega10_set_mclk_od()  argument
4554 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_mclk_od()
4560 	ps = hwmgr->request_ps;  in vega10_set_mclk_od()
4577 			hwmgr->platform_descriptor.overdriveLimit.memoryClock)  in vega10_set_mclk_od()
4580 				hwmgr->platform_descriptor.overdriveLimit.memoryClock;  in vega10_set_mclk_od()
4585 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,  in vega10_notify_cac_buffer_info()  argument
4592 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_notify_cac_buffer_info()
4595 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_notify_cac_buffer_info()
4598 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_notify_cac_buffer_info()
4602 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_notify_cac_buffer_info()
4606 	smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_notify_cac_buffer_info()
4612 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,  in vega10_get_thermal_temperature_range()  argument
4616 			(struct phm_ppt_v2_information *)hwmgr->pptable;  in vega10_get_thermal_temperature_range()
4626 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)  in vega10_get_power_profile_mode()  argument
4628 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_get_power_profile_mode()
4657 			i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",  in vega10_get_power_profile_mode()
4661 			profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",  in vega10_get_power_profile_mode()
4667 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)  in vega10_set_power_profile_mode()  argument
4669 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_set_power_profile_mode()
4675 	hwmgr->power_profile_mode = input[size];  in vega10_set_power_profile_mode()
4677 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,  in vega10_set_power_profile_mode()
4678 						1<<hwmgr->power_profile_mode);  in vega10_set_power_profile_mode()
4680 	if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {  in vega10_set_power_profile_mode()
4688 		smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_set_power_profile_mode()
4698 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,  in vega10_check_clk_voltage_valid()  argument
4703 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_check_clk_voltage_valid()
4715 			hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {  in vega10_check_clk_voltage_valid()
4718 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);  in vega10_check_clk_voltage_valid()
4724 			hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {  in vega10_check_clk_voltage_valid()
4727 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);  in vega10_check_clk_voltage_valid()
4737 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,  in vega10_odn_update_soc_table()  argument
4740 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_odn_update_soc_table()
4741 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;  in vega10_odn_update_soc_table()
4796 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,  in vega10_odn_edit_dpm_table()  argument
4800 	struct vega10_hwmgr *data = hwmgr->backend;  in vega10_odn_edit_dpm_table()
4812 	if (!hwmgr->od_enabled) {  in vega10_odn_edit_dpm_table()
4827 		vega10_odn_initial_default_setting(hwmgr);  in vega10_odn_edit_dpm_table()
4830 		vega10_check_dpm_table_updated(hwmgr);  in vega10_odn_edit_dpm_table()
4845 		if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {  in vega10_odn_edit_dpm_table()
4853 	vega10_odn_update_soc_table(hwmgr, type);  in vega10_odn_edit_dpm_table()
4918 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,  in vega10_enable_smc_features()  argument
4924 	return smum_send_msg_to_smc_with_parameter(hwmgr,  in vega10_enable_smc_features()
4928 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)  in vega10_hwmgr_init()  argument
4930 	hwmgr->hwmgr_func = &vega10_hwmgr_funcs;  in vega10_hwmgr_init()
4931 	hwmgr->pptable_func = &vega10_pptable_funcs;  in vega10_hwmgr_init()