Lines Matching refs:hwmgr
68 static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, in smu8_get_eclk_level() argument
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
99 static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, in smu8_get_sclk_level() argument
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
129 static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, in smu8_get_uvd_level() argument
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_get_uvd_level()
160 static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) in smu8_get_max_sclk_level() argument
162 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_max_sclk_level()
165 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel); in smu8_get_max_sclk_level()
166 data->max_sclk_level = smum_get_argument(hwmgr) + 1; in smu8_get_max_sclk_level()
172 static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) in smu8_initialize_dpm_defaults() argument
174 struct smu8_hwmgr *data = hwmgr->backend; in smu8_initialize_dpm_defaults()
175 struct amdgpu_device *adev = hwmgr->adev; in smu8_initialize_dpm_defaults()
197 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
203 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
208 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
215 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
218 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
220 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
228 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
240 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_initialize_dpm_defaults()
249 struct pp_hwmgr *hwmgr, uint16_t voltage) in smu8_convert_8Bit_index_to_voltage() argument
254 static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, in smu8_construct_max_power_limits_table() argument
257 struct smu8_hwmgr *data = hwmgr->backend; in smu8_construct_max_power_limits_table()
260 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
264 table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr, in smu8_construct_max_power_limits_table()
272 struct pp_hwmgr *hwmgr, in smu8_init_dynamic_state_adjustment_rule_settings() argument
304 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu8_init_dynamic_state_adjustment_rule_settings()
309 static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr) in smu8_get_system_info_data() argument
311 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_system_info_data()
318 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev, in smu8_get_system_info_data()
398 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in smu8_get_system_info_data()
404 smu8_construct_max_power_limits_table (hwmgr, in smu8_get_system_info_data()
405 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu8_get_system_info_data()
407 smu8_init_dynamic_state_adjustment_rule_settings(hwmgr, in smu8_get_system_info_data()
413 static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr) in smu8_construct_boot_state() argument
415 struct smu8_hwmgr *data = hwmgr->backend; in smu8_construct_boot_state()
435 static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) in smu8_upload_pptable_to_smu() argument
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
448 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
450 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
452 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
454 if (!hwmgr->need_pp_table_upload) in smu8_upload_pptable_to_smu()
457 ret = smum_download_powerplay_table(hwmgr, &table); in smu8_upload_pptable_to_smu()
484 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
501 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
515 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
527 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
541 atomctrl_get_engine_pll_dividers_kong(hwmgr, in smu8_upload_pptable_to_smu()
549 ret = smum_upload_powerplay_table(hwmgr); in smu8_upload_pptable_to_smu()
554 static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr) in smu8_init_sclk_limit() argument
556 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_sclk_limit()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
567 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_init_sclk_limit()
580 static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) in smu8_init_uvd_limit() argument
582 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_uvd_limit()
584 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_init_uvd_limit()
593 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel); in smu8_init_uvd_limit()
594 level = smum_get_argument(hwmgr); in smu8_init_uvd_limit()
607 static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr) in smu8_init_vce_limit() argument
609 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_vce_limit()
611 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_init_vce_limit()
620 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel); in smu8_init_vce_limit()
621 level = smum_get_argument(hwmgr); in smu8_init_vce_limit()
634 static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) in smu8_init_acp_limit() argument
636 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_acp_limit()
638 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_init_acp_limit()
647 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel); in smu8_init_acp_limit()
648 level = smum_get_argument(hwmgr); in smu8_init_acp_limit()
660 static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr) in smu8_init_power_gate_state() argument
662 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_power_gate_state()
671 static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr) in smu8_init_sclk_threshold() argument
673 struct smu8_hwmgr *data = hwmgr->backend; in smu8_init_sclk_threshold()
678 static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr) in smu8_update_sclk_limit() argument
680 struct smu8_hwmgr *data = hwmgr->backend; in smu8_update_sclk_limit()
682 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
690 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_update_sclk_limit()
697 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
704 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_update_sclk_limit()
706 smu8_get_sclk_level(hwmgr, in smu8_update_sclk_limit()
714 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_update_sclk_limit()
718 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * in smu8_update_sclk_limit()
727 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_update_sclk_limit()
729 smu8_get_sclk_level(hwmgr, in smu8_update_sclk_limit()
734 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_update_sclk_limit()
738 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_update_sclk_limit()
740 smu8_get_sclk_level(hwmgr, in smu8_update_sclk_limit()
748 static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) in smu8_set_deep_sleep_sclk_threshold() argument
750 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_set_deep_sleep_sclk_threshold()
752 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
758 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_set_deep_sleep_sclk_threshold()
766 static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr) in smu8_set_watermark_threshold() argument
769 hwmgr->backend; in smu8_set_watermark_threshold()
771 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_set_watermark_threshold()
778 static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) in smu8_nbdpm_pstate_enable_disable() argument
780 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_nbdpm_pstate_enable_disable()
786 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_nbdpm_pstate_enable_disable()
792 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_nbdpm_pstate_enable_disable()
801 static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr) in smu8_disable_nb_dpm() argument
805 struct smu8_hwmgr *data = hwmgr->backend; in smu8_disable_nb_dpm()
809 smu8_nbdpm_pstate_enable_disable(hwmgr, true, true); in smu8_disable_nb_dpm()
812 hwmgr, in smu8_disable_nb_dpm()
822 static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr) in smu8_enable_nb_dpm() argument
826 struct smu8_hwmgr *data = hwmgr->backend; in smu8_enable_nb_dpm()
833 hwmgr, in smu8_enable_nb_dpm()
843 static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input) in smu8_update_low_mem_pstate() argument
847 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_update_low_mem_pstate()
856 smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch); in smu8_update_low_mem_pstate()
858 smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch); in smu8_update_low_mem_pstate()
860 smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch); in smu8_update_low_mem_pstate()
865 static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) in smu8_set_power_state_tasks() argument
869 smu8_update_sclk_limit(hwmgr); in smu8_set_power_state_tasks()
870 smu8_set_deep_sleep_sclk_threshold(hwmgr); in smu8_set_power_state_tasks()
871 smu8_set_watermark_threshold(hwmgr); in smu8_set_power_state_tasks()
872 ret = smu8_enable_nb_dpm(hwmgr); in smu8_set_power_state_tasks()
875 smu8_update_low_mem_pstate(hwmgr, input); in smu8_set_power_state_tasks()
881 static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr) in smu8_setup_asic_task() argument
885 ret = smu8_upload_pptable_to_smu(hwmgr); in smu8_setup_asic_task()
888 ret = smu8_init_sclk_limit(hwmgr); in smu8_setup_asic_task()
891 ret = smu8_init_uvd_limit(hwmgr); in smu8_setup_asic_task()
894 ret = smu8_init_vce_limit(hwmgr); in smu8_setup_asic_task()
897 ret = smu8_init_acp_limit(hwmgr); in smu8_setup_asic_task()
901 smu8_init_power_gate_state(hwmgr); in smu8_setup_asic_task()
902 smu8_init_sclk_threshold(hwmgr); in smu8_setup_asic_task()
907 static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr) in smu8_power_up_display_clock_sys_pll() argument
909 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_power_up_display_clock_sys_pll()
915 static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr) in smu8_clear_nb_dpm_flag() argument
917 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_clear_nb_dpm_flag()
922 static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr) in smu8_reset_cc6_data() argument
924 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_reset_cc6_data()
932 static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) in smu8_power_off_asic() argument
934 smu8_power_up_display_clock_sys_pll(hwmgr); in smu8_power_off_asic()
935 smu8_clear_nb_dpm_flag(hwmgr); in smu8_power_off_asic()
936 smu8_reset_cc6_data(hwmgr); in smu8_power_off_asic()
940 static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr) in smu8_program_voting_clients() argument
942 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu8_program_voting_clients()
947 static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr) in smu8_clear_voting_clients() argument
949 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu8_clear_voting_clients()
953 static int smu8_start_dpm(struct pp_hwmgr *hwmgr) in smu8_start_dpm() argument
955 struct smu8_hwmgr *data = hwmgr->backend; in smu8_start_dpm()
959 return smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_start_dpm()
964 static int smu8_stop_dpm(struct pp_hwmgr *hwmgr) in smu8_stop_dpm() argument
967 struct smu8_hwmgr *data = hwmgr->backend; in smu8_stop_dpm()
973 ret = smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_stop_dpm()
980 static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr) in smu8_program_bootup_state() argument
982 struct smu8_hwmgr *data = hwmgr->backend; in smu8_program_bootup_state()
987 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_program_bootup_state()
989 smu8_get_sclk_level(hwmgr, in smu8_program_bootup_state()
993 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_program_bootup_state()
995 smu8_get_sclk_level(hwmgr, in smu8_program_bootup_state()
1002 static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) in smu8_reset_acp_boot_level() argument
1004 struct smu8_hwmgr *data = hwmgr->backend; in smu8_reset_acp_boot_level()
1009 static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu8_disable_dpm_tasks() argument
1011 smu8_disable_nb_dpm(hwmgr); in smu8_disable_dpm_tasks()
1013 smu8_clear_voting_clients(hwmgr); in smu8_disable_dpm_tasks()
1014 if (smu8_stop_dpm(hwmgr)) in smu8_disable_dpm_tasks()
1020 static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) in smu8_enable_dpm_tasks() argument
1022 smu8_program_voting_clients(hwmgr); in smu8_enable_dpm_tasks()
1023 if (smu8_start_dpm(hwmgr)) in smu8_enable_dpm_tasks()
1025 smu8_program_bootup_state(hwmgr); in smu8_enable_dpm_tasks()
1026 smu8_reset_acp_boot_level(hwmgr); in smu8_enable_dpm_tasks()
1031 static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, in smu8_apply_state_adjust_rules() argument
1041 struct smu8_hwmgr *data = hwmgr->backend; in smu8_apply_state_adjust_rules()
1049 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1050 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1054 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) in smu8_apply_state_adjust_rules()
1055 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; in smu8_apply_state_adjust_rules()
1058 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
1062 if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) in smu8_apply_state_adjust_rules()
1063 smu8_nbdpm_pstate_enable_disable(hwmgr, false, false); in smu8_apply_state_adjust_rules()
1064 else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) in smu8_apply_state_adjust_rules()
1065 smu8_nbdpm_pstate_enable_disable(hwmgr, false, true); in smu8_apply_state_adjust_rules()
1076 static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr) in smu8_hwmgr_backend_init() argument
1085 hwmgr->backend = data; in smu8_hwmgr_backend_init()
1087 result = smu8_initialize_dpm_defaults(hwmgr); in smu8_hwmgr_backend_init()
1093 result = smu8_get_system_info_data(hwmgr); in smu8_hwmgr_backend_init()
1099 smu8_construct_boot_state(hwmgr); in smu8_hwmgr_backend_init()
1101 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS; in smu8_hwmgr_backend_init()
1106 static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) in smu8_hwmgr_backend_fini() argument
1108 if (hwmgr != NULL) { in smu8_hwmgr_backend_fini()
1109 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu8_hwmgr_backend_fini()
1110 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu8_hwmgr_backend_fini()
1112 kfree(hwmgr->backend); in smu8_hwmgr_backend_fini()
1113 hwmgr->backend = NULL; in smu8_hwmgr_backend_fini()
1118 static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) in smu8_phm_force_dpm_highest() argument
1120 struct smu8_hwmgr *data = hwmgr->backend; in smu8_phm_force_dpm_highest()
1122 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_highest()
1124 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_highest()
1128 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_highest()
1130 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_highest()
1137 static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) in smu8_phm_unforce_dpm_levels() argument
1139 struct smu8_hwmgr *data = hwmgr->backend; in smu8_phm_unforce_dpm_levels()
1141 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1149 hwmgr->pstate_sclk = table->entries[0].clk; in smu8_phm_unforce_dpm_levels()
1150 hwmgr->pstate_mclk = 0; in smu8_phm_unforce_dpm_levels()
1152 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_phm_unforce_dpm_levels()
1162 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_unforce_dpm_levels()
1164 smu8_get_sclk_level(hwmgr, in smu8_phm_unforce_dpm_levels()
1168 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_unforce_dpm_levels()
1170 smu8_get_sclk_level(hwmgr, in smu8_phm_unforce_dpm_levels()
1177 static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) in smu8_phm_force_dpm_lowest() argument
1179 struct smu8_hwmgr *data = hwmgr->backend; in smu8_phm_force_dpm_lowest()
1181 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_lowest()
1183 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_lowest()
1187 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_phm_force_dpm_lowest()
1189 smu8_get_sclk_level(hwmgr, in smu8_phm_force_dpm_lowest()
1196 static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, in smu8_dpm_force_dpm_level() argument
1204 ret = smu8_phm_force_dpm_highest(hwmgr); in smu8_dpm_force_dpm_level()
1209 ret = smu8_phm_force_dpm_lowest(hwmgr); in smu8_dpm_force_dpm_level()
1212 ret = smu8_phm_unforce_dpm_levels(hwmgr); in smu8_dpm_force_dpm_level()
1223 static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) in smu8_dpm_powerdown_uvd() argument
1226 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF); in smu8_dpm_powerdown_uvd()
1230 static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) in smu8_dpm_powerup_uvd() argument
1234 hwmgr, in smu8_dpm_powerup_uvd()
1242 static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) in smu8_dpm_update_vce_dpm() argument
1244 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_update_vce_dpm()
1246 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_dpm_update_vce_dpm()
1250 hwmgr->en_umd_pstate) { in smu8_dpm_update_vce_dpm()
1254 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_vce_dpm()
1256 smu8_get_eclk_level(hwmgr, in smu8_dpm_update_vce_dpm()
1261 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_vce_dpm()
1265 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_vce_dpm()
1271 static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) in smu8_dpm_powerdown_vce() argument
1274 return smum_send_msg_to_smc(hwmgr, in smu8_dpm_powerdown_vce()
1279 static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr) in smu8_dpm_powerup_vce() argument
1282 return smum_send_msg_to_smc(hwmgr, in smu8_dpm_powerup_vce()
1287 static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) in smu8_dpm_get_mclk() argument
1289 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_get_mclk()
1294 static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) in smu8_dpm_get_sclk() argument
1299 if (hwmgr == NULL) in smu8_dpm_get_sclk()
1302 ps = hwmgr->request_ps; in smu8_dpm_get_sclk()
1315 static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, in smu8_dpm_patch_boot_state() argument
1318 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_patch_boot_state()
1330 struct pp_hwmgr *hwmgr, in smu8_dpm_get_pp_table_entry_callback() argument
1340 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_dpm_get_pp_table_entry_callback()
1343 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) in smu8_dpm_get_pp_table_entry_callback()
1344 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); in smu8_dpm_get_pp_table_entry_callback()
1351 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { in smu8_dpm_get_pp_table_entry_callback()
1359 static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) in smu8_dpm_get_num_of_pp_table_entries() argument
1364 result = pp_tables_get_num_of_entries(hwmgr, &ret); in smu8_dpm_get_num_of_pp_table_entries()
1369 static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, in smu8_dpm_get_pp_table_entry() argument
1379 result = pp_tables_get_entry(hwmgr, entry, ps, in smu8_dpm_get_pp_table_entry()
1388 static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr) in smu8_get_power_state_size() argument
1408 static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr) in smu8_set_cpu_power_state() argument
1410 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_set_cpu_power_state()
1432 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_set_cpu_power_state()
1441 static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, in smu8_store_cc6_data() argument
1444 struct smu8_hwmgr *hw_data = hwmgr->backend; in smu8_store_cc6_data()
1468 static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr, in smu8_get_dal_power_level() argument
1473 hwmgr->dyn_state.vddc_dep_on_dal_pwrl; in smu8_get_dal_power_level()
1475 &hwmgr->dyn_state.max_clock_voltage_on_ac; in smu8_get_dal_power_level()
1489 static int smu8_force_clock_level(struct pp_hwmgr *hwmgr, in smu8_force_clock_level() argument
1494 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_force_clock_level()
1497 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_force_clock_level()
1508 static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, in smu8_print_clock_levels() argument
1511 struct smu8_hwmgr *data = hwmgr->backend; in smu8_print_clock_levels()
1513 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels()
1518 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1530 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1547 static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, in smu8_get_performance_level() argument
1556 if (level == NULL || hwmgr == NULL || state == NULL) in smu8_get_performance_level()
1559 data = hwmgr->backend; in smu8_get_performance_level()
1579 …level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) /… in smu8_get_performance_level()
1586 static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, in smu8_get_current_shallow_sleep_clocks() argument
1597 static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, in smu8_get_clock_by_type() argument
1600 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_clock_by_type()
1604 clocks->count = smu8_get_max_sclk_level(hwmgr); in smu8_get_clock_by_type()
1611 table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_clock_by_type()
1627 static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) in smu8_get_max_high_clocks() argument
1630 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_max_high_clocks()
1633 &hwmgr->dyn_state.max_clock_voltage_on_ac; in smu8_get_max_high_clocks()
1638 level = smu8_get_max_sclk_level(hwmgr) - 1; in smu8_get_max_high_clocks()
1650 static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr) in smu8_thermal_get_temperature() argument
1653 uint32_t val = cgs_read_ind_register(hwmgr->device, in smu8_thermal_get_temperature()
1665 static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, in smu8_read_sensor() argument
1668 struct smu8_hwmgr *data = hwmgr->backend; in smu8_read_sensor()
1671 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_read_sensor()
1674 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_read_sensor()
1677 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_read_sensor()
1679 …uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGE… in smu8_read_sensor()
1681 …uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1683 …uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1704 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & in smu8_read_sensor()
1706 vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4; in smu8_read_sensor()
1710 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & in smu8_read_sensor()
1712 vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4; in smu8_read_sensor()
1752 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity); in smu8_read_sensor()
1754 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0); in smu8_read_sensor()
1768 *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); in smu8_read_sensor()
1775 static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, in smu8_notify_cac_buffer_info() argument
1782 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1785 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1788 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1791 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1795 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_notify_cac_buffer_info()
1801 static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, in smu8_get_thermal_temperature_range() argument
1804 struct smu8_hwmgr *data = hwmgr->backend; in smu8_get_thermal_temperature_range()
1815 static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu8_enable_disable_uvd_dpm() argument
1817 struct smu8_hwmgr *data = hwmgr->backend; in smu8_enable_disable_uvd_dpm()
1821 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu8_enable_disable_uvd_dpm()
1825 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_uvd_dpm()
1830 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_uvd_dpm()
1836 int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_update_uvd_dpm() argument
1838 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_update_uvd_dpm()
1840 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_dpm_update_uvd_dpm()
1845 hwmgr->en_umd_pstate) { in smu8_dpm_update_uvd_dpm()
1849 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_dpm_update_uvd_dpm()
1851 smu8_get_uvd_level(hwmgr, in smu8_dpm_update_uvd_dpm()
1855 smu8_enable_disable_uvd_dpm(hwmgr, true); in smu8_dpm_update_uvd_dpm()
1857 smu8_enable_disable_uvd_dpm(hwmgr, true); in smu8_dpm_update_uvd_dpm()
1860 smu8_enable_disable_uvd_dpm(hwmgr, false); in smu8_dpm_update_uvd_dpm()
1866 static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu8_enable_disable_vce_dpm() argument
1868 struct smu8_hwmgr *data = hwmgr->backend; in smu8_enable_disable_vce_dpm()
1872 hwmgr->platform_descriptor.platformCaps, in smu8_enable_disable_vce_dpm()
1876 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_vce_dpm()
1881 smum_send_msg_to_smc_with_parameter(hwmgr, in smu8_enable_disable_vce_dpm()
1889 static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_powergate_uvd() argument
1891 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_powergate_uvd()
1896 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1899 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1902 smu8_dpm_update_uvd_dpm(hwmgr, true); in smu8_dpm_powergate_uvd()
1903 smu8_dpm_powerdown_uvd(hwmgr); in smu8_dpm_powergate_uvd()
1905 smu8_dpm_powerup_uvd(hwmgr); in smu8_dpm_powergate_uvd()
1906 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1909 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_uvd()
1912 smu8_dpm_update_uvd_dpm(hwmgr, false); in smu8_dpm_powergate_uvd()
1917 static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) in smu8_dpm_powergate_vce() argument
1919 struct smu8_hwmgr *data = hwmgr->backend; in smu8_dpm_powergate_vce()
1922 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
1925 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
1928 smu8_enable_disable_vce_dpm(hwmgr, false); in smu8_dpm_powergate_vce()
1929 smu8_dpm_powerdown_vce(hwmgr); in smu8_dpm_powergate_vce()
1932 smu8_dpm_powerup_vce(hwmgr); in smu8_dpm_powergate_vce()
1934 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
1937 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in smu8_dpm_powergate_vce()
1940 smu8_dpm_update_vce_dpm(hwmgr); in smu8_dpm_powergate_vce()
1941 smu8_enable_disable_vce_dpm(hwmgr, true); in smu8_dpm_powergate_vce()
1978 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr) in smu8_init_function_pointers() argument
1980 hwmgr->hwmgr_func = &smu8_hwmgr_funcs; in smu8_init_function_pointers()
1981 hwmgr->pptable_func = &pptable_funcs; in smu8_init_function_pointers()