28 static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)  in smu7_enable_disable_uvd_dpm()  argument
30 	return smum_send_msg_to_smc(hwmgr, enable ?  in smu7_enable_disable_uvd_dpm()
35 static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)  in smu7_enable_disable_vce_dpm()  argument
37 	return smum_send_msg_to_smc(hwmgr, enable ?  in smu7_enable_disable_vce_dpm()
42 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_update_uvd_dpm()  argument
45 		smum_update_smc_table(hwmgr, SMU_UVD_TABLE);  in smu7_update_uvd_dpm()
46 	return smu7_enable_disable_uvd_dpm(hwmgr, !bgate);  in smu7_update_uvd_dpm()
49 static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_update_vce_dpm()  argument
52 		smum_update_smc_table(hwmgr, SMU_VCE_TABLE);  in smu7_update_vce_dpm()
53 	return smu7_enable_disable_vce_dpm(hwmgr, !bgate);  in smu7_update_vce_dpm()
56 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)  in smu7_powerdown_uvd()  argument
58 	if (phm_cf_want_uvd_power_gating(hwmgr))  in smu7_powerdown_uvd()
59 		return smum_send_msg_to_smc(hwmgr,  in smu7_powerdown_uvd()
64 static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)  in smu7_powerup_uvd()  argument
66 	if (phm_cf_want_uvd_power_gating(hwmgr)) {  in smu7_powerup_uvd()
67 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,  in smu7_powerup_uvd()
69 			return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_powerup_uvd()
72 			return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_powerup_uvd()
80 static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)  in smu7_powerdown_vce()  argument
82 	if (phm_cf_want_vce_power_gating(hwmgr))  in smu7_powerdown_vce()
83 		return smum_send_msg_to_smc(hwmgr,  in smu7_powerdown_vce()
88 static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)  in smu7_powerup_vce()  argument
90 	if (phm_cf_want_vce_power_gating(hwmgr))  in smu7_powerup_vce()
91 		return smum_send_msg_to_smc(hwmgr,  in smu7_powerup_vce()
96 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)  in smu7_disable_clock_power_gating()  argument
98 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);  in smu7_disable_clock_power_gating()
103 	smu7_powerup_uvd(hwmgr);  in smu7_disable_clock_power_gating()
104 	smu7_powerup_vce(hwmgr);  in smu7_disable_clock_power_gating()
109 void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_powergate_uvd()  argument
111 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);  in smu7_powergate_uvd()
116 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_uvd()
119 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_uvd()
122 		smu7_update_uvd_dpm(hwmgr, true);  in smu7_powergate_uvd()
123 		smu7_powerdown_uvd(hwmgr);  in smu7_powergate_uvd()
125 		smu7_powerup_uvd(hwmgr);  in smu7_powergate_uvd()
126 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_uvd()
129 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_uvd()
132 		smu7_update_uvd_dpm(hwmgr, false);  in smu7_powergate_uvd()
137 void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)  in smu7_powergate_vce()  argument
139 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);  in smu7_powergate_vce()
144 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_vce()
147 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_vce()
150 		smu7_update_vce_dpm(hwmgr, true);  in smu7_powergate_vce()
151 		smu7_powerdown_vce(hwmgr);  in smu7_powergate_vce()
153 		smu7_powerup_vce(hwmgr);  in smu7_powergate_vce()
154 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,  in smu7_powergate_vce()
157 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu7_powergate_vce()
160 		smu7_update_vce_dpm(hwmgr, false);  in smu7_powergate_vce()
164 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,  in smu7_update_clock_gatings()  argument
170 	if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))  in smu7_update_clock_gatings()
184 						hwmgr, msg, value))  in smu7_update_clock_gatings()
194 						hwmgr, msg, value))  in smu7_update_clock_gatings()
207 						hwmgr, msg, value))  in smu7_update_clock_gatings()
218 						hwmgr, msg, value))  in smu7_update_clock_gatings()
231 						hwmgr, msg, value))  in smu7_update_clock_gatings()
244 						hwmgr, msg, value))  in smu7_update_clock_gatings()
258 						hwmgr, msg, value))  in smu7_update_clock_gatings()
278 						hwmgr, msg, value))  in smu7_update_clock_gatings()
288 						hwmgr, msg, value))  in smu7_update_clock_gatings()
301 						hwmgr, msg, value))  in smu7_update_clock_gatings()
312 						hwmgr, msg, value))  in smu7_update_clock_gatings()
325 						hwmgr, msg, value))  in smu7_update_clock_gatings()
335 						hwmgr, msg, value))  in smu7_update_clock_gatings()
348 						hwmgr, msg, value))  in smu7_update_clock_gatings()
359 						hwmgr, msg, value))  in smu7_update_clock_gatings()
372 						hwmgr, msg, value))  in smu7_update_clock_gatings()
383 						hwmgr, msg, value))  in smu7_update_clock_gatings()
396 						hwmgr, msg, value))  in smu7_update_clock_gatings()
419 int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)  in smu7_powergate_gfx()  argument
421 	struct amdgpu_device *adev = hwmgr->adev;  in smu7_powergate_gfx()
424 		return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu7_powergate_gfx()
428 		return smum_send_msg_to_smc(hwmgr,  in smu7_powergate_gfx()