55 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,  in smu10_display_clock_voltage_request()  argument
58 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_display_clock_voltage_request()
83 	smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);  in smu10_display_clock_voltage_request()
105 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)  in smu10_initialize_dpm_defaults()  argument
107 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_initialize_dpm_defaults()
117 	if (hwmgr->feature_mask & PP_GFXOFF_MASK)  in smu10_initialize_dpm_defaults()
122 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in smu10_initialize_dpm_defaults()
125 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in smu10_initialize_dpm_defaults()
128 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in smu10_initialize_dpm_defaults()
133 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,  in smu10_construct_max_power_limits_table()  argument
140 							struct pp_hwmgr *hwmgr)  in smu10_init_dynamic_state_adjustment_rule_settings()  argument
171 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;  in smu10_init_dynamic_state_adjustment_rule_settings()
176 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)  in smu10_get_system_info_data()  argument
178 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;  in smu10_get_system_info_data()
186 	smu10_construct_max_power_limits_table (hwmgr,  in smu10_get_system_info_data()
187 				    &hwmgr->dyn_state.max_clock_voltage_on_ac);  in smu10_get_system_info_data()
189 	smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);  in smu10_get_system_info_data()
194 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)  in smu10_construct_boot_state()  argument
199 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)  in smu10_set_clock_limit()  argument
204 	clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;  in smu10_set_clock_limit()
208 	PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),  in smu10_set_clock_limit()
214 static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)  in smu10_set_deep_sleep_dcefclk()  argument
216 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_set_deep_sleep_dcefclk()
220 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_set_deep_sleep_dcefclk()
227 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)  in smu10_set_active_display_count()  argument
229 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_set_active_display_count()
233 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_set_active_display_count()
241 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)  in smu10_set_power_state_tasks()  argument
243 	return smu10_set_clock_limit(hwmgr, input);  in smu10_set_power_state_tasks()
246 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)  in smu10_init_power_gate_state()  argument
248 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_init_power_gate_state()
249 	struct amdgpu_device *adev = hwmgr->adev;  in smu10_init_power_gate_state()
256 		return smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_init_power_gate_state()
264 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)  in smu10_setup_asic_task()  argument
266 	return smu10_init_power_gate_state(hwmgr);  in smu10_setup_asic_task()
269 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)  in smu10_reset_cc6_data()  argument
271 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_reset_cc6_data()
281 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)  in smu10_power_off_asic()  argument
283 	return smu10_reset_cc6_data(hwmgr);  in smu10_power_off_asic()
286 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)  in smu10_is_gfx_on()  argument
289 	struct amdgpu_device *adev = hwmgr->adev;  in smu10_is_gfx_on()
299 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)  in smu10_disable_gfx_off()  argument
301 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_disable_gfx_off()
304 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);  in smu10_disable_gfx_off()
307 		while (!smu10_is_gfx_on(hwmgr))  in smu10_disable_gfx_off()
314 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)  in smu10_disable_dpm_tasks()  argument
319 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)  in smu10_enable_gfx_off()  argument
321 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_enable_gfx_off()
324 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);  in smu10_enable_gfx_off()
329 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)  in smu10_enable_dpm_tasks()  argument
334 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)  in smu10_gfx_off_control()  argument
337 		return smu10_enable_gfx_off(hwmgr);  in smu10_gfx_off_control()
339 		return smu10_disable_gfx_off(hwmgr);  in smu10_gfx_off_control()
342 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,  in smu10_apply_state_adjust_rules()  argument
386 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,  in smu10_get_clock_voltage_dependency_table()  argument
413 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)  in smu10_populate_clock_table()  argument
417 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_populate_clock_table()
421 	result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);  in smu10_populate_clock_table()
428 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,  in smu10_populate_clock_table()
431 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,  in smu10_populate_clock_table()
434 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,  in smu10_populate_clock_table()
437 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,  in smu10_populate_clock_table()
441 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,  in smu10_populate_clock_table()
444 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,  in smu10_populate_clock_table()
447 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,  in smu10_populate_clock_table()
451 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,  in smu10_populate_clock_table()
454 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,  in smu10_populate_clock_table()
456 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,  in smu10_populate_clock_table()
459 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);  in smu10_populate_clock_table()
460 	result = smum_get_argument(hwmgr);  in smu10_populate_clock_table()
463 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);  in smu10_populate_clock_table()
464 	result = smum_get_argument(hwmgr);  in smu10_populate_clock_table()
470 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)  in smu10_hwmgr_backend_init()  argument
479 	hwmgr->backend = data;  in smu10_hwmgr_backend_init()
481 	result = smu10_initialize_dpm_defaults(hwmgr);  in smu10_hwmgr_backend_init()
487 	smu10_populate_clock_table(hwmgr);  in smu10_hwmgr_backend_init()
489 	result = smu10_get_system_info_data(hwmgr);  in smu10_hwmgr_backend_init()
495 	smu10_construct_boot_state(hwmgr);  in smu10_hwmgr_backend_init()
497 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  in smu10_hwmgr_backend_init()
500 	hwmgr->platform_descriptor.hardwarePerformanceLevels =  in smu10_hwmgr_backend_init()
503 	hwmgr->platform_descriptor.vbiosInterruptId = 0;  in smu10_hwmgr_backend_init()
505 	hwmgr->platform_descriptor.clockStep.engineClock = 500;  in smu10_hwmgr_backend_init()
507 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;  in smu10_hwmgr_backend_init()
509 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;  in smu10_hwmgr_backend_init()
511 	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;  in smu10_hwmgr_backend_init()
512 	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;  in smu10_hwmgr_backend_init()
517 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)  in smu10_hwmgr_backend_fini()  argument
519 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_hwmgr_backend_fini()
535 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);  in smu10_hwmgr_backend_fini()
536 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;  in smu10_hwmgr_backend_fini()
538 	kfree(hwmgr->backend);  in smu10_hwmgr_backend_fini()
539 	hwmgr->backend = NULL;  in smu10_hwmgr_backend_fini()
544 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,  in smu10_dpm_force_dpm_level()  argument
547 	struct smu10_hwmgr *data = hwmgr->backend;  in smu10_dpm_force_dpm_level()
549 	if (hwmgr->smu_version < 0x1E3700) {  in smu10_dpm_force_dpm_level()
557 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
560 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
563 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
566 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
570 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
573 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
576 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
579 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
584 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
587 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
592 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
595 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
600 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
603 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
606 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
609 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
613 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
616 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
619 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
622 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
627 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
630 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
632 						hwmgr->display_config->num_display > 3 ?  in smu10_dpm_force_dpm_level()
636 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
639 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
643 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
646 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
649 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
652 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
657 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
660 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
663 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
666 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_dpm_force_dpm_level()
678 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)  in smu10_dpm_get_mclk()  argument
682 	if (hwmgr == NULL)  in smu10_dpm_get_mclk()
685 	data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_dpm_get_mclk()
694 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)  in smu10_dpm_get_sclk()  argument
698 	if (hwmgr == NULL)  in smu10_dpm_get_sclk()
701 	data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_dpm_get_sclk()
709 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,  in smu10_dpm_patch_boot_state()  argument
716 						     struct pp_hwmgr *hwmgr,  in smu10_dpm_get_pp_table_entry_callback()  argument
728 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {  in smu10_dpm_get_pp_table_entry_callback()
736 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)  in smu10_dpm_get_num_of_pp_table_entries()  argument
741 	result = pp_tables_get_num_of_entries(hwmgr, &ret);  in smu10_dpm_get_num_of_pp_table_entries()
746 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,  in smu10_dpm_get_pp_table_entry()  argument
756 	result = pp_tables_get_entry(hwmgr, entry, ps,  in smu10_dpm_get_pp_table_entry()
765 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)  in smu10_get_power_state_size()  argument
770 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)  in smu10_set_cpu_power_state()  argument
776 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,  in smu10_store_cc6_data()  argument
779 	struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_store_cc6_data()
792 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,  in smu10_get_dal_power_level()  argument
798 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,  in smu10_force_clock_level()  argument
801 	struct smu10_hwmgr *data = hwmgr->backend;  in smu10_force_clock_level()
816 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_force_clock_level()
822 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_force_clock_level()
833 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_force_clock_level()
837 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_force_clock_level()
849 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,  in smu10_print_clock_levels()  argument
852 	struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_print_clock_levels()
859 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);  in smu10_print_clock_levels()
860 		now = smum_get_argument(hwmgr);  in smu10_print_clock_levels()
881 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);  in smu10_print_clock_levels()
882 		now = smum_get_argument(hwmgr);  in smu10_print_clock_levels()
898 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *stat…  in smu10_get_performance_level()  argument
904 	if (level == NULL || hwmgr == NULL || state == NULL)  in smu10_get_performance_level()
907 	data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_get_performance_level()
924 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,  in smu10_get_current_shallow_sleep_clocks()  argument
942 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,  in smu10_get_mem_latency()  argument
954 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,  in smu10_get_clock_by_type_with_latency()  argument
959 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_get_clock_by_type_with_latency()
998 						smu10_get_mem_latency(hwmgr,  in smu10_get_clock_by_type_with_latency()
1007 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,  in smu10_get_clock_by_type_with_voltage()  argument
1012 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);  in smu10_get_clock_by_type_with_voltage()
1057 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clock…  in smu10_get_max_high_clocks()  argument
1063 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)  in smu10_thermal_get_temperature()  argument
1065 	struct amdgpu_device *adev = hwmgr->adev;  in smu10_thermal_get_temperature()
1078 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,  in smu10_read_sensor()  argument
1086 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);  in smu10_read_sensor()
1087 		sclk = smum_get_argument(hwmgr);  in smu10_read_sensor()
1093 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);  in smu10_read_sensor()
1094 		mclk = smum_get_argument(hwmgr);  in smu10_read_sensor()
1100 		*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);  in smu10_read_sensor()
1110 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,  in smu10_set_watermarks_for_clocks_ranges()  argument
1113 	struct smu10_hwmgr *data = hwmgr->backend;  in smu10_set_watermarks_for_clocks_ranges()
1119 	smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);  in smu10_set_watermarks_for_clocks_ranges()
1124 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)  in smu10_smus_notify_pwe()  argument
1127 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister);  in smu10_smus_notify_pwe()
1130 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)  in smu10_powergate_mmhub()  argument
1132 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);  in smu10_powergate_mmhub()
1135 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)  in smu10_powergate_vcn()  argument
1138 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu10_powergate_vcn()
1141 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_powergate_vcn()
1144 		smum_send_msg_to_smc_with_parameter(hwmgr,  in smu10_powergate_vcn()
1146 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,  in smu10_powergate_vcn()
1193 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)  in smu10_init_function_pointers()  argument
1195 	hwmgr->hwmgr_func = &smu10_hwmgr_funcs;  in smu10_init_function_pointers()
1196 	hwmgr->pptable_func = &pptable_funcs;  in smu10_init_function_pointers()