1301 		const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 =  in init_clock_voltage_dependency()  local
1303 		if (0 != powerplay_table4->usVddcDependencyOnSCLKOffset) {  in init_clock_voltage_dependency()
1305 				(((unsigned long) powerplay_table4) +  in init_clock_voltage_dependency()
1306 				powerplay_table4->usVddcDependencyOnSCLKOffset);  in init_clock_voltage_dependency()
1311 		if (result == 0 && (0 != powerplay_table4->usVddciDependencyOnMCLKOffset)) {  in init_clock_voltage_dependency()
1313 				(((unsigned long) powerplay_table4) +  in init_clock_voltage_dependency()
1314 				powerplay_table4->usVddciDependencyOnMCLKOffset);  in init_clock_voltage_dependency()
1319 		if (result == 0 && (0 != powerplay_table4->usVddcDependencyOnMCLKOffset)) {  in init_clock_voltage_dependency()
1321 				(((unsigned long) powerplay_table4) +  in init_clock_voltage_dependency()
1322 				powerplay_table4->usVddcDependencyOnMCLKOffset);  in init_clock_voltage_dependency()
1327 		if (result == 0 && (0 != powerplay_table4->usMaxClockVoltageOnDCOffset)) {  in init_clock_voltage_dependency()
1329 				(((unsigned long) powerplay_table4) +  in init_clock_voltage_dependency()
1330 				powerplay_table4->usMaxClockVoltageOnDCOffset);  in init_clock_voltage_dependency()
1346 		if (result == 0 && (0 != powerplay_table4->usMvddDependencyOnMCLKOffset)) {  in init_clock_voltage_dependency()
1348 				(((unsigned long) powerplay_table4) +  in init_clock_voltage_dependency()
1349 				powerplay_table4->usMvddDependencyOnMCLKOffset);  in init_clock_voltage_dependency()
1507 		const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 =  in init_phase_shedding_table()  local
1510 		if (0 != powerplay_table4->usVddcPhaseShedLimitsTableOffset) {  in init_phase_shedding_table()
1513 				(((unsigned long)powerplay_table4) +  in init_phase_shedding_table()
1514 				le16_to_cpu(powerplay_table4->usVddcPhaseShedLimitsTableOffset));  in init_phase_shedding_table()