48 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr,  in get_vce_table_offset()  argument
72 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr,  in get_vce_clock_info_array_offset()  argument
75 	uint16_t table_offset = get_vce_table_offset(hwmgr,  in get_vce_clock_info_array_offset()
84 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr,  in get_vce_clock_info_array_size()  argument
87 	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,  in get_vce_clock_info_array_size()
100 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr,  in get_vce_clock_voltage_limit_table_offset()  argument
103 	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,  in get_vce_clock_voltage_limit_table_offset()
107 		return table_offset + get_vce_clock_info_array_size(hwmgr,  in get_vce_clock_voltage_limit_table_offset()
113 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr,  in get_vce_clock_voltage_limit_table_size()  argument
116 	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);  in get_vce_clock_voltage_limit_table_size()
128 static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE …  in get_vce_state_table_offset()  argument
130 	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);  in get_vce_state_table_offset()
133 		return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);  in get_vce_state_table_offset()
139 						struct pp_hwmgr *hwmgr,  in get_vce_state_table()  argument
142 	uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);  in get_vce_state_table()
150 static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr,  in get_uvd_table_offset()  argument
172 static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr,  in get_uvd_clock_info_array_offset()  argument
175 	uint16_t table_offset = get_uvd_table_offset(hwmgr,  in get_uvd_clock_info_array_offset()
183 static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr,  in get_uvd_clock_info_array_size()  argument
186 	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,  in get_uvd_clock_info_array_size()
202 			struct pp_hwmgr *hwmgr,  in get_uvd_clock_voltage_limit_table_offset()  argument
205 	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,  in get_uvd_clock_voltage_limit_table_offset()
210 			get_uvd_clock_info_array_size(hwmgr, powerplay_table);  in get_uvd_clock_voltage_limit_table_offset()
215 static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr,  in get_samu_table_offset()  argument
239 			struct pp_hwmgr *hwmgr,  in get_samu_clock_voltage_limit_table_offset()  argument
242 	uint16_t table_offset = get_samu_table_offset(hwmgr,  in get_samu_clock_voltage_limit_table_offset()
251 static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr,  in get_acp_table_offset()  argument
275 				struct pp_hwmgr *hwmgr,  in get_acp_clock_voltage_limit_table_offset()  argument
278 	uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table);  in get_acp_clock_voltage_limit_table_offset()
287 				struct pp_hwmgr *hwmgr,  in get_cacp_tdp_table_offset()  argument
310 static int get_cac_tdp_table(struct pp_hwmgr *hwmgr,  in get_cac_tdp_table()  argument
338 static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr,  in get_sclk_vdd_gfx_table_offset()  argument
363 			struct pp_hwmgr *hwmgr,  in get_sclk_vdd_gfx_clock_voltage_dependency_table_offset()  argument
366 	uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table);  in get_sclk_vdd_gfx_clock_voltage_dependency_table_offset()
375 static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,  in get_clock_voltage_dependency_table()  argument
406 static int get_valid_clk(struct pp_hwmgr *hwmgr,  in get_valid_clk()  argument
428 static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr,  in get_clock_voltage_limit()  argument
443 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,  in set_hw_cap()  argument
447 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);  in set_hw_cap()
449 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);  in set_hw_cap()
452 static int set_platform_caps(struct pp_hwmgr *hwmgr,  in set_platform_caps()  argument
456 		hwmgr,  in set_platform_caps()
462 		hwmgr,  in set_platform_caps()
468 		hwmgr,  in set_platform_caps()
474 		hwmgr,  in set_platform_caps()
480 		hwmgr,  in set_platform_caps()
486 		hwmgr,  in set_platform_caps()
492 		hwmgr,  in set_platform_caps()
498 		hwmgr,  in set_platform_caps()
504 		hwmgr,  in set_platform_caps()
510 		hwmgr,  in set_platform_caps()
516 		hwmgr,  in set_platform_caps()
522 		hwmgr,  in set_platform_caps()
528 		hwmgr,  in set_platform_caps()
534 		hwmgr,  in set_platform_caps()
540 		hwmgr,  in set_platform_caps()
546 		hwmgr,  in set_platform_caps()
552 		hwmgr,  in set_platform_caps()
558 		hwmgr,  in set_platform_caps()
564 		hwmgr,  in set_platform_caps()
570 		hwmgr,  in set_platform_caps()
576 		hwmgr,  in set_platform_caps()
582 		hwmgr,  in set_platform_caps()
588 		hwmgr,  in set_platform_caps()
594 		hwmgr,  in set_platform_caps()
600 		hwmgr,  in set_platform_caps()
606 		hwmgr,  in set_platform_caps()
612 		hwmgr,  in set_platform_caps()
621 						   struct pp_hwmgr *hwmgr,  in make_classification_flags()  argument
678 static int init_non_clock_fields(struct pp_hwmgr *hwmgr,  in init_non_clock_fields()  argument
687 	ps->classification.flags = make_classification_flags(hwmgr,  in init_non_clock_fields()
828 				     struct pp_hwmgr *hwmgr)  in get_powerplay_table()  argument
830 	const void *table_addr = hwmgr->soft_pp_table;  in get_powerplay_table()
835 		if (hwmgr->chip_id == CHIP_RAVEN) {  in get_powerplay_table()
837 			hwmgr->soft_pp_table = &soft_dummy_pp_table[0];  in get_powerplay_table()
838 			hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);  in get_powerplay_table()
840 			table_addr = smu_atom_get_data_table(hwmgr->adev,  in get_powerplay_table()
843 			hwmgr->soft_pp_table = table_addr;  in get_powerplay_table()
844 			hwmgr->soft_pp_table_size = size;  in get_powerplay_table()
851 int pp_tables_get_response_times(struct pp_hwmgr *hwmgr,  in pp_tables_get_response_times()  argument
854 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr);  in pp_tables_get_response_times()
865 int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,  in pp_tables_get_num_of_entries()  argument
869 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);  in pp_tables_get_num_of_entries()
885 int pp_tables_get_entry(struct pp_hwmgr *hwmgr,  in pp_tables_get_entry()  argument
894 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);  in pp_tables_get_entry()
926 		result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info);  in pp_tables_get_entry()
932 			res = func(hwmgr, &ps->hardware, i, pclock_info);  in pp_tables_get_entry()
948 		result = init_non_clock_fields(hwmgr, ps,  in pp_tables_get_entry()
958 			int res = func(hwmgr, &ps->hardware, i, pclock_info);  in pp_tables_get_entry()
966 		if (hwmgr->chip_family < AMDGPU_FAMILY_RV)  in pp_tables_get_entry()
967 			result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));  in pp_tables_get_entry()
974 			struct pp_hwmgr *hwmgr,  in init_powerplay_tables()  argument
983 			struct pp_hwmgr *hwmgr,  in init_thermal_controller()  argument
989 static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr,  in init_overdrive_limits_V1_4()  argument
993 	hwmgr->platform_descriptor.overdriveLimit.engineClock =  in init_overdrive_limits_V1_4()
996 	hwmgr->platform_descriptor.overdriveLimit.memoryClock =  in init_overdrive_limits_V1_4()
999 	hwmgr->platform_descriptor.maxOverdriveVDDC =  in init_overdrive_limits_V1_4()
1002 	hwmgr->platform_descriptor.minOverdriveVDDC =  in init_overdrive_limits_V1_4()
1005 	hwmgr->platform_descriptor.maxOverdriveVDDC =  in init_overdrive_limits_V1_4()
1008 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;  in init_overdrive_limits_V1_4()
1012 static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr,  in init_overdrive_limits_V2_1()  argument
1031 	hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock);  in init_overdrive_limits_V2_1()
1032 	hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock);  in init_overdrive_limits_V2_1()
1035 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;  in init_overdrive_limits_V2_1()
1036 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;  in init_overdrive_limits_V2_1()
1037 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;  in init_overdrive_limits_V2_1()
1042 static int init_overdrive_limits(struct pp_hwmgr *hwmgr,  in init_overdrive_limits()  argument
1051 	hwmgr->platform_descriptor.overdriveLimit.engineClock = 0;  in init_overdrive_limits()
1052 	hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0;  in init_overdrive_limits()
1053 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;  in init_overdrive_limits()
1054 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;  in init_overdrive_limits()
1055 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;  in init_overdrive_limits()
1057 	if (hwmgr->chip_id == CHIP_RAVEN)  in init_overdrive_limits()
1061 	fw_info = smu_atom_get_data_table(hwmgr->adev,  in init_overdrive_limits()
1067 		result = init_overdrive_limits_V1_4(hwmgr,  in init_overdrive_limits()
1073 		result = init_overdrive_limits_V2_1(hwmgr,  in init_overdrive_limits()
1080 static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,  in get_uvd_clock_voltage_limit_table()  argument
1113 static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,  in get_vce_clock_voltage_limit_table()  argument
1145 static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,  in get_samu_clock_voltage_limit_table()  argument
1173 static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,  in get_acp_clock_voltage_limit_table()  argument
1201 static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,  in init_clock_voltage_dependency()  argument
1212 	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;  in init_clock_voltage_dependency()
1213 	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;  in init_clock_voltage_dependency()
1214 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;  in init_clock_voltage_dependency()
1215 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;  in init_clock_voltage_dependency()
1216 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;  in init_clock_voltage_dependency()
1217 	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;  in init_clock_voltage_dependency()
1218 	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;  in init_clock_voltage_dependency()
1219 	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;  in init_clock_voltage_dependency()
1220 	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;  in init_clock_voltage_dependency()
1221 	hwmgr->dyn_state.ppm_parameter_table = NULL;  in init_clock_voltage_dependency()
1222 	hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;  in init_clock_voltage_dependency()
1225 						hwmgr, powerplay_table);  in init_clock_voltage_dependency()
1226 	table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr,  in init_clock_voltage_dependency()
1235 		result = get_vce_clock_voltage_limit_table(hwmgr,  in init_clock_voltage_dependency()
1236 				&hwmgr->dyn_state.vce_clock_voltage_dependency_table,  in init_clock_voltage_dependency()
1240 	uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table);  in init_clock_voltage_dependency()
1241 	table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table);  in init_clock_voltage_dependency()
1250 		result = get_uvd_clock_voltage_limit_table(hwmgr,  in init_clock_voltage_dependency()
1251 				&hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array);  in init_clock_voltage_dependency()
1254 	table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,  in init_clock_voltage_dependency()
1261 		result = get_samu_clock_voltage_limit_table(hwmgr,  in init_clock_voltage_dependency()
1262 				&hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable);  in init_clock_voltage_dependency()
1265 	table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr,  in init_clock_voltage_dependency()
1272 		result = get_acp_clock_voltage_limit_table(hwmgr,  in init_clock_voltage_dependency()
1273 				&hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable);  in init_clock_voltage_dependency()
1276 	table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table);  in init_clock_voltage_dependency()
1284 			result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table,  in init_clock_voltage_dependency()
1287 			hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =  in init_clock_voltage_dependency()
1293 			result = get_cac_tdp_table(hwmgr,  in init_clock_voltage_dependency()
1294 				&hwmgr->dyn_state.cac_dtp_table,  in init_clock_voltage_dependency()
1307 			result = get_clock_voltage_dependency_table(hwmgr,  in init_clock_voltage_dependency()
1308 				&hwmgr->dyn_state.vddc_dependency_on_sclk, table);  in init_clock_voltage_dependency()
1315 			result = get_clock_voltage_dependency_table(hwmgr,  in init_clock_voltage_dependency()
1316 				&hwmgr->dyn_state.vddci_dependency_on_mclk, table);  in init_clock_voltage_dependency()
1323 			result = get_clock_voltage_dependency_table(hwmgr,  in init_clock_voltage_dependency()
1324 				&hwmgr->dyn_state.vddc_dependency_on_mclk, table);  in init_clock_voltage_dependency()
1331 			result = get_clock_voltage_limit(hwmgr,  in init_clock_voltage_dependency()
1332 				&hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table);  in init_clock_voltage_dependency()
1335 		if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) &&  in init_clock_voltage_dependency()
1336 			(0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count))  in init_clock_voltage_dependency()
1337 			result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values,  in init_clock_voltage_dependency()
1338 					hwmgr->dyn_state.vddc_dependency_on_mclk);  in init_clock_voltage_dependency()
1340 		if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) &&  in init_clock_voltage_dependency()
1341 			(0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count))  in init_clock_voltage_dependency()
1342 			result = get_valid_clk(hwmgr,  in init_clock_voltage_dependency()
1343 				&hwmgr->dyn_state.valid_sclk_values,  in init_clock_voltage_dependency()
1344 				hwmgr->dyn_state.vddc_dependency_on_sclk);  in init_clock_voltage_dependency()
1350 			result = get_clock_voltage_dependency_table(hwmgr,  in init_clock_voltage_dependency()
1351 				&hwmgr->dyn_state.mvdd_dependency_on_mclk, table);  in init_clock_voltage_dependency()
1355 	table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr,  in init_clock_voltage_dependency()
1361 		result = get_clock_voltage_dependency_table(hwmgr,  in init_clock_voltage_dependency()
1362 			&hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table);  in init_clock_voltage_dependency()
1368 static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,  in get_cac_leakage_table()  argument
1375 	if (hwmgr == NULL || table == NULL || ptable == NULL)  in get_cac_leakage_table()
1389 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,  in get_cac_leakage_table()
1405 static int get_platform_power_management_table(struct pp_hwmgr *hwmgr,  in get_platform_power_management_table()  argument
1423 	hwmgr->dyn_state.ppm_parameter_table = ptr;  in get_platform_power_management_table()
1428 static int init_dpm2_parameters(struct pp_hwmgr *hwmgr,  in init_dpm2_parameters()  argument
1447 		hwmgr->platform_descriptor.TDPLimit     = le32_to_cpu(ptable5->ulTDPLimit);  in init_dpm2_parameters()
1448 		hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit);  in init_dpm2_parameters()
1450 		hwmgr->platform_descriptor.TDPODLimit   = le16_to_cpu(ptable5->usTDPODLimit);  in init_dpm2_parameters()
1451 		hwmgr->platform_descriptor.TDPAdjustment = 0;  in init_dpm2_parameters()
1453 		hwmgr->platform_descriptor.VidAdjustment = 0;  in init_dpm2_parameters()
1454 		hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;  in init_dpm2_parameters()
1455 		hwmgr->platform_descriptor.VidMinLimit     = 0;  in init_dpm2_parameters()
1456 		hwmgr->platform_descriptor.VidMaxLimit     = 1500000;  in init_dpm2_parameters()
1457 		hwmgr->platform_descriptor.VidStep         = 6250;  in init_dpm2_parameters()
1459 		hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit);  in init_dpm2_parameters()
1461 		if (hwmgr->platform_descriptor.TDPODLimit != 0)  in init_dpm2_parameters()
1462 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in init_dpm2_parameters()
1465 		hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold);  in init_dpm2_parameters()
1467 		hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage);  in init_dpm2_parameters()
1469 		hwmgr->dyn_state.cac_leakage_table = NULL;  in init_dpm2_parameters()
1475 			result = get_cac_leakage_table(hwmgr,  in init_dpm2_parameters()
1476 				&hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table);  in init_dpm2_parameters()
1479 		hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope);  in init_dpm2_parameters()
1481 		hwmgr->dyn_state.ppm_parameter_table = NULL;  in init_dpm2_parameters()
1493 				if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table))  in init_dpm2_parameters()
1494 					phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in init_dpm2_parameters()
1502 static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,  in init_phase_shedding_table()  argument
1537 			hwmgr->dyn_state.vddc_phase_shed_limits_table = table;  in init_phase_shedding_table()
1545 						  struct pp_hwmgr *hwmgr)  in get_number_of_vce_state_table_entries()  argument
1548 					     get_powerplay_table(hwmgr);  in get_number_of_vce_state_table_entries()
1550 				    get_vce_state_table(hwmgr, table);  in get_number_of_vce_state_table_entries()
1558 static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,  in get_vce_state_table_entry()  argument
1564 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);  in get_vce_state_table_entry()
1566 	const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table);  in get_vce_state_table_entry()
1568 …unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_tabl…  in get_vce_state_table_entry()
1591 static int pp_tables_initialize(struct pp_hwmgr *hwmgr)  in pp_tables_initialize()  argument
1596 	if (hwmgr->chip_id == CHIP_RAVEN)  in pp_tables_initialize()
1599 	hwmgr->need_pp_table_upload = true;  in pp_tables_initialize()
1601 	powerplay_table = get_powerplay_table(hwmgr);  in pp_tables_initialize()
1603 	result = init_powerplay_tables(hwmgr, powerplay_table);  in pp_tables_initialize()
1608 	result = set_platform_caps(hwmgr,  in pp_tables_initialize()
1614 	result = init_thermal_controller(hwmgr, powerplay_table);  in pp_tables_initialize()
1619 	result = init_overdrive_limits(hwmgr, powerplay_table);  in pp_tables_initialize()
1624 	result = init_clock_voltage_dependency(hwmgr,  in pp_tables_initialize()
1630 	result = init_dpm2_parameters(hwmgr, powerplay_table);  in pp_tables_initialize()
1635 	result = init_phase_shedding_table(hwmgr, powerplay_table);  in pp_tables_initialize()
1643 static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)  in pp_tables_uninitialize()  argument
1645 	if (hwmgr->chip_id == CHIP_RAVEN)  in pp_tables_uninitialize()
1648 	kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);  in pp_tables_uninitialize()
1649 	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;  in pp_tables_uninitialize()
1651 	kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);  in pp_tables_uninitialize()
1652 	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;  in pp_tables_uninitialize()
1654 	kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);  in pp_tables_uninitialize()
1655 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;  in pp_tables_uninitialize()
1657 	kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);  in pp_tables_uninitialize()
1658 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;  in pp_tables_uninitialize()
1660 	kfree(hwmgr->dyn_state.valid_mclk_values);  in pp_tables_uninitialize()
1661 	hwmgr->dyn_state.valid_mclk_values = NULL;  in pp_tables_uninitialize()
1663 	kfree(hwmgr->dyn_state.valid_sclk_values);  in pp_tables_uninitialize()
1664 	hwmgr->dyn_state.valid_sclk_values = NULL;  in pp_tables_uninitialize()
1666 	kfree(hwmgr->dyn_state.cac_leakage_table);  in pp_tables_uninitialize()
1667 	hwmgr->dyn_state.cac_leakage_table = NULL;  in pp_tables_uninitialize()
1669 	kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);  in pp_tables_uninitialize()
1670 	hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;  in pp_tables_uninitialize()
1672 	kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);  in pp_tables_uninitialize()
1673 	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;  in pp_tables_uninitialize()
1675 	kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);  in pp_tables_uninitialize()
1676 	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;  in pp_tables_uninitialize()
1678 	kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);  in pp_tables_uninitialize()
1679 	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;  in pp_tables_uninitialize()
1681 	kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);  in pp_tables_uninitialize()
1682 	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;  in pp_tables_uninitialize()
1684 	kfree(hwmgr->dyn_state.cac_dtp_table);  in pp_tables_uninitialize()
1685 	hwmgr->dyn_state.cac_dtp_table = NULL;  in pp_tables_uninitialize()
1687 	kfree(hwmgr->dyn_state.ppm_parameter_table);  in pp_tables_uninitialize()
1688 	hwmgr->dyn_state.ppm_parameter_table = NULL;  in pp_tables_uninitialize()
1690 	kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);  in pp_tables_uninitialize()
1691 	hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;  in pp_tables_uninitialize()