Lines Matching refs:dyn_state
1212 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1213 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1214 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1215 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1216 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1217 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1218 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1219 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1220 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1221 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
1222 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1236 &hwmgr->dyn_state.vce_clock_voltage_dependency_table, in init_clock_voltage_dependency()
1251 &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array); in init_clock_voltage_dependency()
1262 &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1273 &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1284 result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1287 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = in init_clock_voltage_dependency()
1294 &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1308 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1316 &hwmgr->dyn_state.vddci_dependency_on_mclk, table); in init_clock_voltage_dependency()
1324 &hwmgr->dyn_state.vddc_dependency_on_mclk, table); in init_clock_voltage_dependency()
1332 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); in init_clock_voltage_dependency()
1335 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && in init_clock_voltage_dependency()
1336 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) in init_clock_voltage_dependency()
1337 result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values, in init_clock_voltage_dependency()
1338 hwmgr->dyn_state.vddc_dependency_on_mclk); in init_clock_voltage_dependency()
1340 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1341 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1343 &hwmgr->dyn_state.valid_sclk_values, in init_clock_voltage_dependency()
1344 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1351 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); in init_clock_voltage_dependency()
1362 &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table); in init_clock_voltage_dependency()
1423 hwmgr->dyn_state.ppm_parameter_table = ptr; in get_platform_power_management_table()
1469 hwmgr->dyn_state.cac_leakage_table = NULL; in init_dpm2_parameters()
1476 &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table); in init_dpm2_parameters()
1481 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_dpm2_parameters()
1537 hwmgr->dyn_state.vddc_phase_shed_limits_table = table; in init_phase_shedding_table()
1648 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1649 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
1651 kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); in pp_tables_uninitialize()
1652 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1654 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); in pp_tables_uninitialize()
1655 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1657 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); in pp_tables_uninitialize()
1658 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1660 kfree(hwmgr->dyn_state.valid_mclk_values); in pp_tables_uninitialize()
1661 hwmgr->dyn_state.valid_mclk_values = NULL; in pp_tables_uninitialize()
1663 kfree(hwmgr->dyn_state.valid_sclk_values); in pp_tables_uninitialize()
1664 hwmgr->dyn_state.valid_sclk_values = NULL; in pp_tables_uninitialize()
1666 kfree(hwmgr->dyn_state.cac_leakage_table); in pp_tables_uninitialize()
1667 hwmgr->dyn_state.cac_leakage_table = NULL; in pp_tables_uninitialize()
1669 kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); in pp_tables_uninitialize()
1670 hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; in pp_tables_uninitialize()
1672 kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); in pp_tables_uninitialize()
1673 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1675 kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); in pp_tables_uninitialize()
1676 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1678 kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); in pp_tables_uninitialize()
1679 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1681 kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); in pp_tables_uninitialize()
1682 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1684 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_uninitialize()
1685 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_uninitialize()
1687 kfree(hwmgr->dyn_state.ppm_parameter_table); in pp_tables_uninitialize()
1688 hwmgr->dyn_state.ppm_parameter_table = NULL; in pp_tables_uninitialize()
1690 kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); in pp_tables_uninitialize()
1691 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in pp_tables_uninitialize()