48 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
49 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
50 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
51 extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
52 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
54 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
55 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
56 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
57 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
58 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
59 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
60 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
63 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)  in hwmgr_init_workload_prority()  argument
65 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;  in hwmgr_init_workload_prority()
66 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;  in hwmgr_init_workload_prority()
67 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;  in hwmgr_init_workload_prority()
68 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;  in hwmgr_init_workload_prority()
69 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;  in hwmgr_init_workload_prority()
71 	hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;  in hwmgr_init_workload_prority()
72 	hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;  in hwmgr_init_workload_prority()
73 	hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;  in hwmgr_init_workload_prority()
74 	hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;  in hwmgr_init_workload_prority()
75 	hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;  in hwmgr_init_workload_prority()
78 int hwmgr_early_init(struct pp_hwmgr *hwmgr)  in hwmgr_early_init()  argument
80 	if (!hwmgr)  in hwmgr_early_init()
83 	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;  in hwmgr_early_init()
84 	hwmgr->pp_table_version = PP_TABLE_V1;  in hwmgr_early_init()
85 	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;  in hwmgr_early_init()
86 	hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;  in hwmgr_early_init()
87 	hwmgr_init_default_caps(hwmgr);  in hwmgr_early_init()
88 	hwmgr_set_user_specify_caps(hwmgr);  in hwmgr_early_init()
89 	hwmgr->fan_ctrl_is_in_default_mode = true;  in hwmgr_early_init()
90 	hwmgr->reload_fw = 1;  in hwmgr_early_init()
91 	hwmgr_init_workload_prority(hwmgr);  in hwmgr_early_init()
93 	switch (hwmgr->chip_family) {  in hwmgr_early_init()
95 		hwmgr->smumgr_funcs = &ci_smu_funcs;  in hwmgr_early_init()
96 		ci_set_asic_special_caps(hwmgr);  in hwmgr_early_init()
97 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |  in hwmgr_early_init()
100 		hwmgr->pp_table_version = PP_TABLE_V0;  in hwmgr_early_init()
101 		hwmgr->od_enabled = false;  in hwmgr_early_init()
102 		smu7_init_function_pointers(hwmgr);  in hwmgr_early_init()
105 		hwmgr->od_enabled = false;  in hwmgr_early_init()
106 		hwmgr->smumgr_funcs = &smu8_smu_funcs;  in hwmgr_early_init()
107 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;  in hwmgr_early_init()
108 		smu8_init_function_pointers(hwmgr);  in hwmgr_early_init()
111 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;  in hwmgr_early_init()
112 		switch (hwmgr->chip_id) {  in hwmgr_early_init()
114 			hwmgr->smumgr_funcs = &iceland_smu_funcs;  in hwmgr_early_init()
115 			topaz_set_asic_special_caps(hwmgr);  in hwmgr_early_init()
116 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |  in hwmgr_early_init()
118 			hwmgr->pp_table_version = PP_TABLE_V0;  in hwmgr_early_init()
119 			hwmgr->od_enabled = false;  in hwmgr_early_init()
122 			hwmgr->smumgr_funcs = &tonga_smu_funcs;  in hwmgr_early_init()
123 			tonga_set_asic_special_caps(hwmgr);  in hwmgr_early_init()
124 			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;  in hwmgr_early_init()
127 			hwmgr->smumgr_funcs = &fiji_smu_funcs;  in hwmgr_early_init()
128 			fiji_set_asic_special_caps(hwmgr);  in hwmgr_early_init()
129 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |  in hwmgr_early_init()
135 			hwmgr->smumgr_funcs = &polaris10_smu_funcs;  in hwmgr_early_init()
136 			polaris_set_asic_special_caps(hwmgr);  in hwmgr_early_init()
137 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);  in hwmgr_early_init()
140 			hwmgr->smumgr_funcs = &vegam_smu_funcs;  in hwmgr_early_init()
141 			polaris_set_asic_special_caps(hwmgr);  in hwmgr_early_init()
142 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);  in hwmgr_early_init()
147 		smu7_init_function_pointers(hwmgr);  in hwmgr_early_init()
150 		switch (hwmgr->chip_id) {  in hwmgr_early_init()
153 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;  in hwmgr_early_init()
154 			hwmgr->smumgr_funcs = &vega10_smu_funcs;  in hwmgr_early_init()
155 			vega10_hwmgr_init(hwmgr);  in hwmgr_early_init()
158 			hwmgr->smumgr_funcs = &vega12_smu_funcs;  in hwmgr_early_init()
159 			vega12_hwmgr_init(hwmgr);  in hwmgr_early_init()
166 		switch (hwmgr->chip_id) {  in hwmgr_early_init()
168 			hwmgr->od_enabled = false;  in hwmgr_early_init()
169 			hwmgr->smumgr_funcs = &smu10_smu_funcs;  in hwmgr_early_init()
170 			smu10_init_function_pointers(hwmgr);  in hwmgr_early_init()
183 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)  in hwmgr_sw_init()  argument
185 	if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)  in hwmgr_sw_init()
188 	phm_register_irq_handlers(hwmgr);  in hwmgr_sw_init()
190 	return hwmgr->smumgr_funcs->smu_init(hwmgr);  in hwmgr_sw_init()
194 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)  in hwmgr_sw_fini()  argument
196 	if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)  in hwmgr_sw_fini()
197 		hwmgr->smumgr_funcs->smu_fini(hwmgr);  in hwmgr_sw_fini()
202 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)  in hwmgr_hw_init()  argument
206 	if (!hwmgr || !hwmgr->smumgr_funcs)  in hwmgr_hw_init()
209 	if (hwmgr->smumgr_funcs->start_smu) {  in hwmgr_hw_init()
210 		ret = hwmgr->smumgr_funcs->start_smu(hwmgr);  in hwmgr_hw_init()
217 	if (!hwmgr->pm_en)  in hwmgr_hw_init()
220 	if (!hwmgr->pptable_func ||  in hwmgr_hw_init()
221 	    !hwmgr->pptable_func->pptable_init ||  in hwmgr_hw_init()
222 	    !hwmgr->hwmgr_func->backend_init) {  in hwmgr_hw_init()
223 		hwmgr->pm_en = false;  in hwmgr_hw_init()
228 	ret = hwmgr->pptable_func->pptable_init(hwmgr);  in hwmgr_hw_init()
232 	((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =  in hwmgr_hw_init()
233 				hwmgr->thermal_controller.fanInfo.bNoFan;  in hwmgr_hw_init()
235 	ret = hwmgr->hwmgr_func->backend_init(hwmgr);  in hwmgr_hw_init()
239 	if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in hwmgr_hw_init()
240 			(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))  in hwmgr_hw_init()
241 			hwmgr->dyn_state.max_clock_voltage_on_dc =  in hwmgr_hw_init()
242 					hwmgr->dyn_state.max_clock_voltage_on_ac;  in hwmgr_hw_init()
244 	ret = psm_init_power_state_table(hwmgr);  in hwmgr_hw_init()
248 	ret = phm_setup_asic(hwmgr);  in hwmgr_hw_init()
252 	ret = phm_enable_dynamic_state_management(hwmgr);  in hwmgr_hw_init()
255 	ret = phm_start_thermal_controller(hwmgr);  in hwmgr_hw_init()
256 	ret |= psm_set_performance_states(hwmgr);  in hwmgr_hw_init()
260 	((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;  in hwmgr_hw_init()
264 	if (hwmgr->hwmgr_func->backend_fini)  in hwmgr_hw_init()
265 		hwmgr->hwmgr_func->backend_fini(hwmgr);  in hwmgr_hw_init()
267 	if (hwmgr->pptable_func->pptable_fini)  in hwmgr_hw_init()
268 		hwmgr->pptable_func->pptable_fini(hwmgr);  in hwmgr_hw_init()
273 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)  in hwmgr_hw_fini()  argument
275 	if (!hwmgr || !hwmgr->pm_en)  in hwmgr_hw_fini()
278 	phm_stop_thermal_controller(hwmgr);  in hwmgr_hw_fini()
279 	psm_set_boot_states(hwmgr);  in hwmgr_hw_fini()
280 	psm_adjust_power_state_dynamic(hwmgr, false, NULL);  in hwmgr_hw_fini()
281 	phm_disable_dynamic_state_management(hwmgr);  in hwmgr_hw_fini()
282 	phm_disable_clock_power_gatings(hwmgr);  in hwmgr_hw_fini()
284 	if (hwmgr->hwmgr_func->backend_fini)  in hwmgr_hw_fini()
285 		hwmgr->hwmgr_func->backend_fini(hwmgr);  in hwmgr_hw_fini()
286 	if (hwmgr->pptable_func->pptable_fini)  in hwmgr_hw_fini()
287 		hwmgr->pptable_func->pptable_fini(hwmgr);  in hwmgr_hw_fini()
288 	return psm_fini_power_state_table(hwmgr);  in hwmgr_hw_fini()
291 int hwmgr_suspend(struct pp_hwmgr *hwmgr)  in hwmgr_suspend()  argument
295 	if (!hwmgr || !hwmgr->pm_en)  in hwmgr_suspend()
298 	phm_disable_smc_firmware_ctf(hwmgr);  in hwmgr_suspend()
299 	ret = psm_set_boot_states(hwmgr);  in hwmgr_suspend()
302 	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);  in hwmgr_suspend()
305 	ret = phm_power_down_asic(hwmgr);  in hwmgr_suspend()
310 int hwmgr_resume(struct pp_hwmgr *hwmgr)  in hwmgr_resume()  argument
314 	if (!hwmgr)  in hwmgr_resume()
317 	if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {  in hwmgr_resume()
318 		if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {  in hwmgr_resume()
324 	if (!hwmgr->pm_en)  in hwmgr_resume()
327 	ret = phm_setup_asic(hwmgr);  in hwmgr_resume()
331 	ret = phm_enable_dynamic_state_management(hwmgr);  in hwmgr_resume()
334 	ret = phm_start_thermal_controller(hwmgr);  in hwmgr_resume()
335 	ret |= psm_set_performance_states(hwmgr);  in hwmgr_resume()
339 	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);  in hwmgr_resume()
358 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,  in hwmgr_handle_task()  argument
363 	if (hwmgr == NULL)  in hwmgr_handle_task()
368 		ret = phm_set_cpu_power_state(hwmgr);  in hwmgr_handle_task()
371 		ret = psm_set_performance_states(hwmgr);  in hwmgr_handle_task()
374 		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);  in hwmgr_handle_task()
387 		ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);  in hwmgr_handle_task()
390 		ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);  in hwmgr_handle_task()
395 		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);  in hwmgr_handle_task()
403 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)  in hwmgr_init_default_caps()  argument
405 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);  in hwmgr_init_default_caps()
407 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);  in hwmgr_init_default_caps()
408 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);  in hwmgr_init_default_caps()
411 	if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))  in hwmgr_init_default_caps()
412 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);  in hwmgr_init_default_caps()
415 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_init_default_caps()
418 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_init_default_caps()
421 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_init_default_caps()
424 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_init_default_caps()
427 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_init_default_caps()
430 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_init_default_caps()
435 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)  in hwmgr_set_user_specify_caps()  argument
437 	if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)  in hwmgr_set_user_specify_caps()
438 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_set_user_specify_caps()
441 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in hwmgr_set_user_specify_caps()
444 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {  in hwmgr_set_user_specify_caps()
445 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_set_user_specify_caps()
447 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in hwmgr_set_user_specify_caps()
450 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in hwmgr_set_user_specify_caps()
452 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in hwmgr_set_user_specify_caps()
456 	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)  in hwmgr_set_user_specify_caps()
457 		hwmgr->od_enabled = true;  in hwmgr_set_user_specify_caps()
462 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)  in polaris_set_asic_special_caps()  argument
464 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
466 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
468 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
471 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
474 	if (hwmgr->chip_id != CHIP_POLARIS10)  in polaris_set_asic_special_caps()
475 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
478 	if (hwmgr->chip_id != CHIP_POLARIS11) {  in polaris_set_asic_special_caps()
479 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
481 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
483 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in polaris_set_asic_special_caps()
489 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)  in fiji_set_asic_special_caps()  argument
491 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in fiji_set_asic_special_caps()
493 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in fiji_set_asic_special_caps()
495 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in fiji_set_asic_special_caps()
497 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in fiji_set_asic_special_caps()
499 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in fiji_set_asic_special_caps()
504 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)  in tonga_set_asic_special_caps()  argument
506 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
508 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
510 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
512 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
514 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
517 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
519 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in tonga_set_asic_special_caps()
524 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)  in topaz_set_asic_special_caps()  argument
526 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in topaz_set_asic_special_caps()
528 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in topaz_set_asic_special_caps()
530 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in topaz_set_asic_special_caps()
532 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in topaz_set_asic_special_caps()
534 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in topaz_set_asic_special_caps()
539 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)  in ci_set_asic_special_caps()  argument
541 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in ci_set_asic_special_caps()
543 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in ci_set_asic_special_caps()
545 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in ci_set_asic_special_caps()
547 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,  in ci_set_asic_special_caps()
549 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in ci_set_asic_special_caps()
551 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,  in ci_set_asic_special_caps()