Lines Matching refs:hwmgr
40 struct pp_hwmgr *hwmgr; in amd_powerplay_create() local
45 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); in amd_powerplay_create()
46 if (hwmgr == NULL) in amd_powerplay_create()
49 hwmgr->adev = adev; in amd_powerplay_create()
50 hwmgr->not_vf = !amdgpu_sriov_vf(adev); in amd_powerplay_create()
51 hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false; in amd_powerplay_create()
52 hwmgr->device = amdgpu_cgs_create_device(adev); in amd_powerplay_create()
53 mutex_init(&hwmgr->smu_lock); in amd_powerplay_create()
54 hwmgr->chip_family = adev->family; in amd_powerplay_create()
55 hwmgr->chip_id = adev->asic_type; in amd_powerplay_create()
56 hwmgr->feature_mask = adev->powerplay.pp_feature; in amd_powerplay_create()
57 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
58 adev->powerplay.pp_handle = hwmgr; in amd_powerplay_create()
66 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amd_powerplay_destroy() local
68 kfree(hwmgr->hardcode_pp_table); in amd_powerplay_destroy()
69 hwmgr->hardcode_pp_table = NULL; in amd_powerplay_destroy()
71 kfree(hwmgr); in amd_powerplay_destroy()
72 hwmgr = NULL; in amd_powerplay_destroy()
95 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_sw_init() local
98 ret = hwmgr_sw_init(hwmgr); in pp_sw_init()
108 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_sw_fini() local
110 hwmgr_sw_fini(hwmgr); in pp_sw_fini()
125 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_hw_init() local
130 ret = hwmgr_hw_init(hwmgr); in pp_hw_init()
141 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_hw_fini() local
143 hwmgr_hw_fini(hwmgr); in pp_hw_fini()
153 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_reserve_vram_for_smu() local
164 if (hwmgr->hwmgr_func->notify_cac_buffer_info) in pp_reserve_vram_for_smu()
165 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, in pp_reserve_vram_for_smu()
182 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_late_init() local
184 if (hwmgr && hwmgr->pm_en) { in pp_late_init()
185 mutex_lock(&hwmgr->smu_lock); in pp_late_init()
186 hwmgr_handle_task(hwmgr, in pp_late_init()
188 mutex_unlock(&hwmgr->smu_lock); in pp_late_init()
230 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_suspend() local
232 return hwmgr_suspend(hwmgr); in pp_suspend()
238 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_resume() local
240 return hwmgr_resume(hwmgr); in pp_resume()
288 struct pp_hwmgr *hwmgr = handle; in pp_set_clockgating_by_smu() local
290 if (!hwmgr || !hwmgr->pm_en) in pp_set_clockgating_by_smu()
293 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { in pp_set_clockgating_by_smu()
298 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); in pp_set_clockgating_by_smu()
301 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, in pp_dpm_en_umd_pstate() argument
309 if (!(hwmgr->dpm_level & profile_mode_mask)) { in pp_dpm_en_umd_pstate()
312 hwmgr->saved_dpm_level = hwmgr->dpm_level; in pp_dpm_en_umd_pstate()
313 hwmgr->en_umd_pstate = true; in pp_dpm_en_umd_pstate()
314 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in pp_dpm_en_umd_pstate()
317 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in pp_dpm_en_umd_pstate()
325 *level = hwmgr->saved_dpm_level; in pp_dpm_en_umd_pstate()
326 hwmgr->en_umd_pstate = false; in pp_dpm_en_umd_pstate()
327 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, in pp_dpm_en_umd_pstate()
330 amdgpu_device_ip_set_powergating_state(hwmgr->adev, in pp_dpm_en_umd_pstate()
340 struct pp_hwmgr *hwmgr = handle; in pp_dpm_force_performance_level() local
342 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_force_performance_level()
345 if (level == hwmgr->dpm_level) in pp_dpm_force_performance_level()
348 mutex_lock(&hwmgr->smu_lock); in pp_dpm_force_performance_level()
349 pp_dpm_en_umd_pstate(hwmgr, &level); in pp_dpm_force_performance_level()
350 hwmgr->request_dpm_level = level; in pp_dpm_force_performance_level()
351 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); in pp_dpm_force_performance_level()
352 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_force_performance_level()
360 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_performance_level() local
363 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_performance_level()
366 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_performance_level()
367 level = hwmgr->dpm_level; in pp_dpm_get_performance_level()
368 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_performance_level()
374 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_sclk() local
377 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_sclk()
380 if (hwmgr->hwmgr_func->get_sclk == NULL) { in pp_dpm_get_sclk()
384 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_sclk()
385 clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low); in pp_dpm_get_sclk()
386 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_sclk()
392 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_mclk() local
395 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_mclk()
398 if (hwmgr->hwmgr_func->get_mclk == NULL) { in pp_dpm_get_mclk()
402 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_mclk()
403 clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low); in pp_dpm_get_mclk()
404 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_mclk()
410 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_vce() local
412 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_vce()
415 if (hwmgr->hwmgr_func->powergate_vce == NULL) { in pp_dpm_powergate_vce()
419 mutex_lock(&hwmgr->smu_lock); in pp_dpm_powergate_vce()
420 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); in pp_dpm_powergate_vce()
421 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_powergate_vce()
426 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_uvd() local
428 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_uvd()
431 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { in pp_dpm_powergate_uvd()
435 mutex_lock(&hwmgr->smu_lock); in pp_dpm_powergate_uvd()
436 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); in pp_dpm_powergate_uvd()
437 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_powergate_uvd()
444 struct pp_hwmgr *hwmgr = handle; in pp_dpm_dispatch_tasks() local
446 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_dispatch_tasks()
449 mutex_lock(&hwmgr->smu_lock); in pp_dpm_dispatch_tasks()
450 ret = hwmgr_handle_task(hwmgr, task_id, user_state); in pp_dpm_dispatch_tasks()
451 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_dispatch_tasks()
458 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_current_power_state() local
462 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) in pp_dpm_get_current_power_state()
465 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_current_power_state()
467 state = hwmgr->current_ps; in pp_dpm_get_current_power_state()
486 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_current_power_state()
493 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_control_mode() local
495 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_control_mode()
498 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { in pp_dpm_set_fan_control_mode()
502 mutex_lock(&hwmgr->smu_lock); in pp_dpm_set_fan_control_mode()
503 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); in pp_dpm_set_fan_control_mode()
504 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_set_fan_control_mode()
509 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_control_mode() local
512 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_control_mode()
515 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) { in pp_dpm_get_fan_control_mode()
519 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_fan_control_mode()
520 mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); in pp_dpm_get_fan_control_mode()
521 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_fan_control_mode()
527 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_speed_percent() local
530 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_speed_percent()
533 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) { in pp_dpm_set_fan_speed_percent()
537 mutex_lock(&hwmgr->smu_lock); in pp_dpm_set_fan_speed_percent()
538 ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent); in pp_dpm_set_fan_speed_percent()
539 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_set_fan_speed_percent()
545 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_speed_percent() local
548 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_speed_percent()
551 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) { in pp_dpm_get_fan_speed_percent()
556 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_fan_speed_percent()
557 ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); in pp_dpm_get_fan_speed_percent()
558 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_fan_speed_percent()
564 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_speed_rpm() local
567 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_speed_rpm()
570 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) in pp_dpm_get_fan_speed_rpm()
573 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_fan_speed_rpm()
574 ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); in pp_dpm_get_fan_speed_rpm()
575 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_fan_speed_rpm()
582 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_pp_num_states() local
587 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps) in pp_dpm_get_pp_num_states()
590 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_pp_num_states()
592 data->nums = hwmgr->num_ps; in pp_dpm_get_pp_num_states()
594 for (i = 0; i < hwmgr->num_ps; i++) { in pp_dpm_get_pp_num_states()
596 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); in pp_dpm_get_pp_num_states()
614 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_pp_num_states()
620 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_pp_table() local
623 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table) in pp_dpm_get_pp_table()
626 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_pp_table()
627 *table = (char *)hwmgr->soft_pp_table; in pp_dpm_get_pp_table()
628 size = hwmgr->soft_pp_table_size; in pp_dpm_get_pp_table()
629 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_pp_table()
635 struct pp_hwmgr *hwmgr = handle; in amd_powerplay_reset() local
638 ret = hwmgr_hw_fini(hwmgr); in amd_powerplay_reset()
642 ret = hwmgr_hw_init(hwmgr); in amd_powerplay_reset()
646 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); in amd_powerplay_reset()
651 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_pp_table() local
654 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_pp_table()
657 mutex_lock(&hwmgr->smu_lock); in pp_dpm_set_pp_table()
658 if (!hwmgr->hardcode_pp_table) { in pp_dpm_set_pp_table()
659 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table, in pp_dpm_set_pp_table()
660 hwmgr->soft_pp_table_size, in pp_dpm_set_pp_table()
662 if (!hwmgr->hardcode_pp_table) in pp_dpm_set_pp_table()
666 memcpy(hwmgr->hardcode_pp_table, buf, size); in pp_dpm_set_pp_table()
668 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; in pp_dpm_set_pp_table()
674 if (hwmgr->hwmgr_func->avfs_control) { in pp_dpm_set_pp_table()
675 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); in pp_dpm_set_pp_table()
679 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_set_pp_table()
682 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_set_pp_table()
689 struct pp_hwmgr *hwmgr = handle; in pp_dpm_force_clock_level() local
692 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_force_clock_level()
695 if (hwmgr->hwmgr_func->force_clock_level == NULL) { in pp_dpm_force_clock_level()
699 mutex_lock(&hwmgr->smu_lock); in pp_dpm_force_clock_level()
700 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_force_clock_level()
701 ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); in pp_dpm_force_clock_level()
704 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_force_clock_level()
711 struct pp_hwmgr *hwmgr = handle; in pp_dpm_print_clock_levels() local
714 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_print_clock_levels()
717 if (hwmgr->hwmgr_func->print_clock_levels == NULL) { in pp_dpm_print_clock_levels()
721 mutex_lock(&hwmgr->smu_lock); in pp_dpm_print_clock_levels()
722 ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); in pp_dpm_print_clock_levels()
723 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_print_clock_levels()
729 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_sclk_od() local
732 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_sclk_od()
735 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { in pp_dpm_get_sclk_od()
739 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_sclk_od()
740 ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr); in pp_dpm_get_sclk_od()
741 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_sclk_od()
747 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_sclk_od() local
750 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_sclk_od()
753 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { in pp_dpm_set_sclk_od()
758 mutex_lock(&hwmgr->smu_lock); in pp_dpm_set_sclk_od()
759 ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); in pp_dpm_set_sclk_od()
760 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_set_sclk_od()
766 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_mclk_od() local
769 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_mclk_od()
772 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { in pp_dpm_get_mclk_od()
776 mutex_lock(&hwmgr->smu_lock); in pp_dpm_get_mclk_od()
777 ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr); in pp_dpm_get_mclk_od()
778 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_get_mclk_od()
784 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_mclk_od() local
787 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_mclk_od()
790 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { in pp_dpm_set_mclk_od()
794 mutex_lock(&hwmgr->smu_lock); in pp_dpm_set_mclk_od()
795 ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); in pp_dpm_set_mclk_od()
796 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_set_mclk_od()
803 struct pp_hwmgr *hwmgr = handle; in pp_dpm_read_sensor() local
806 if (!hwmgr || !hwmgr->pm_en || !value) in pp_dpm_read_sensor()
811 *((uint32_t *)value) = hwmgr->pstate_sclk; in pp_dpm_read_sensor()
814 *((uint32_t *)value) = hwmgr->pstate_mclk; in pp_dpm_read_sensor()
817 mutex_lock(&hwmgr->smu_lock); in pp_dpm_read_sensor()
818 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); in pp_dpm_read_sensor()
819 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_read_sensor()
827 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_vce_clock_state() local
829 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_vce_clock_state()
832 if (idx < hwmgr->num_vce_state_tables) in pp_dpm_get_vce_clock_state()
833 return &hwmgr->vce_states[idx]; in pp_dpm_get_vce_clock_state()
839 struct pp_hwmgr *hwmgr = handle; in pp_get_power_profile_mode() local
841 if (!hwmgr || !hwmgr->pm_en || !buf) in pp_get_power_profile_mode()
844 if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) { in pp_get_power_profile_mode()
849 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); in pp_get_power_profile_mode()
854 struct pp_hwmgr *hwmgr = handle; in pp_set_power_profile_mode() local
857 if (!hwmgr || !hwmgr->pm_en) in pp_set_power_profile_mode()
860 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { in pp_set_power_profile_mode()
864 mutex_lock(&hwmgr->smu_lock); in pp_set_power_profile_mode()
865 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) in pp_set_power_profile_mode()
866 ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); in pp_set_power_profile_mode()
867 mutex_unlock(&hwmgr->smu_lock); in pp_set_power_profile_mode()
873 struct pp_hwmgr *hwmgr = handle; in pp_odn_edit_dpm_table() local
875 if (!hwmgr || !hwmgr->pm_en) in pp_odn_edit_dpm_table()
878 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { in pp_odn_edit_dpm_table()
883 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); in pp_odn_edit_dpm_table()
889 struct pp_hwmgr *hwmgr = handle; in pp_dpm_switch_power_profile() local
893 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_switch_power_profile()
896 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { in pp_dpm_switch_power_profile()
904 mutex_lock(&hwmgr->smu_lock); in pp_dpm_switch_power_profile()
907 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); in pp_dpm_switch_power_profile()
908 index = fls(hwmgr->workload_mask); in pp_dpm_switch_power_profile()
910 workload = hwmgr->workload_setting[index]; in pp_dpm_switch_power_profile()
912 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); in pp_dpm_switch_power_profile()
913 index = fls(hwmgr->workload_mask); in pp_dpm_switch_power_profile()
915 workload = hwmgr->workload_setting[index]; in pp_dpm_switch_power_profile()
918 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_switch_power_profile()
919 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); in pp_dpm_switch_power_profile()
920 mutex_unlock(&hwmgr->smu_lock); in pp_dpm_switch_power_profile()
927 struct pp_hwmgr *hwmgr = handle; in pp_set_power_limit() local
929 if (!hwmgr || !hwmgr->pm_en) in pp_set_power_limit()
932 if (hwmgr->hwmgr_func->set_power_limit == NULL) { in pp_set_power_limit()
938 limit = hwmgr->default_power_limit; in pp_set_power_limit()
940 if (limit > hwmgr->default_power_limit) in pp_set_power_limit()
943 mutex_lock(&hwmgr->smu_lock); in pp_set_power_limit()
944 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); in pp_set_power_limit()
945 hwmgr->power_limit = limit; in pp_set_power_limit()
946 mutex_unlock(&hwmgr->smu_lock); in pp_set_power_limit()
952 struct pp_hwmgr *hwmgr = handle; in pp_get_power_limit() local
954 if (!hwmgr || !hwmgr->pm_en ||!limit) in pp_get_power_limit()
957 mutex_lock(&hwmgr->smu_lock); in pp_get_power_limit()
960 *limit = hwmgr->default_power_limit; in pp_get_power_limit()
962 *limit = hwmgr->power_limit; in pp_get_power_limit()
964 mutex_unlock(&hwmgr->smu_lock); in pp_get_power_limit()
972 struct pp_hwmgr *hwmgr = handle; in pp_display_configuration_change() local
974 if (!hwmgr || !hwmgr->pm_en) in pp_display_configuration_change()
977 mutex_lock(&hwmgr->smu_lock); in pp_display_configuration_change()
978 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
979 mutex_unlock(&hwmgr->smu_lock); in pp_display_configuration_change()
986 struct pp_hwmgr *hwmgr = handle; in pp_get_display_power_level() local
989 if (!hwmgr || !hwmgr->pm_en ||!output) in pp_get_display_power_level()
992 mutex_lock(&hwmgr->smu_lock); in pp_get_display_power_level()
993 ret = phm_get_dal_power_level(hwmgr, output); in pp_get_display_power_level()
994 mutex_unlock(&hwmgr->smu_lock); in pp_get_display_power_level()
1003 struct pp_hwmgr *hwmgr = handle; in pp_get_current_clocks() local
1006 if (!hwmgr || !hwmgr->pm_en) in pp_get_current_clocks()
1009 mutex_lock(&hwmgr->smu_lock); in pp_get_current_clocks()
1011 phm_get_dal_power_level(hwmgr, &simple_clocks); in pp_get_current_clocks()
1013 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in pp_get_current_clocks()
1015 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, in pp_get_current_clocks()
1018 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, in pp_get_current_clocks()
1023 mutex_unlock(&hwmgr->smu_lock); in pp_get_current_clocks()
1042 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { in pp_get_current_clocks()
1046 mutex_unlock(&hwmgr->smu_lock); in pp_get_current_clocks()
1052 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type() local
1055 if (!hwmgr || !hwmgr->pm_en) in pp_get_clock_by_type()
1061 mutex_lock(&hwmgr->smu_lock); in pp_get_clock_by_type()
1062 ret = phm_get_clock_by_type(hwmgr, type, clocks); in pp_get_clock_by_type()
1063 mutex_unlock(&hwmgr->smu_lock); in pp_get_clock_by_type()
1071 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type_with_latency() local
1074 if (!hwmgr || !hwmgr->pm_en ||!clocks) in pp_get_clock_by_type_with_latency()
1077 mutex_lock(&hwmgr->smu_lock); in pp_get_clock_by_type_with_latency()
1078 ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks); in pp_get_clock_by_type_with_latency()
1079 mutex_unlock(&hwmgr->smu_lock); in pp_get_clock_by_type_with_latency()
1087 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type_with_voltage() local
1090 if (!hwmgr || !hwmgr->pm_en ||!clocks) in pp_get_clock_by_type_with_voltage()
1093 mutex_lock(&hwmgr->smu_lock); in pp_get_clock_by_type_with_voltage()
1095 ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); in pp_get_clock_by_type_with_voltage()
1097 mutex_unlock(&hwmgr->smu_lock); in pp_get_clock_by_type_with_voltage()
1104 struct pp_hwmgr *hwmgr = handle; in pp_set_watermarks_for_clocks_ranges() local
1107 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) in pp_set_watermarks_for_clocks_ranges()
1110 mutex_lock(&hwmgr->smu_lock); in pp_set_watermarks_for_clocks_ranges()
1111 ret = phm_set_watermarks_for_clocks_ranges(hwmgr, in pp_set_watermarks_for_clocks_ranges()
1113 mutex_unlock(&hwmgr->smu_lock); in pp_set_watermarks_for_clocks_ranges()
1121 struct pp_hwmgr *hwmgr = handle; in pp_display_clock_voltage_request() local
1124 if (!hwmgr || !hwmgr->pm_en ||!clock) in pp_display_clock_voltage_request()
1127 mutex_lock(&hwmgr->smu_lock); in pp_display_clock_voltage_request()
1128 ret = phm_display_clock_voltage_request(hwmgr, clock); in pp_display_clock_voltage_request()
1129 mutex_unlock(&hwmgr->smu_lock); in pp_display_clock_voltage_request()
1137 struct pp_hwmgr *hwmgr = handle; in pp_get_display_mode_validation_clocks() local
1140 if (!hwmgr || !hwmgr->pm_en ||!clocks) in pp_get_display_mode_validation_clocks()
1145 mutex_lock(&hwmgr->smu_lock); in pp_get_display_mode_validation_clocks()
1147 …if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerSta… in pp_get_display_mode_validation_clocks()
1148 ret = phm_get_max_high_clocks(hwmgr, clocks); in pp_get_display_mode_validation_clocks()
1150 mutex_unlock(&hwmgr->smu_lock); in pp_get_display_mode_validation_clocks()
1156 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_mmhub() local
1158 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_mmhub()
1161 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { in pp_dpm_powergate_mmhub()
1166 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); in pp_dpm_powergate_mmhub()
1171 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_gfx() local
1173 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_gfx()
1176 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { in pp_dpm_powergate_gfx()
1181 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); in pp_dpm_powergate_gfx()
1211 struct pp_hwmgr *hwmgr = handle; in pp_notify_smu_enable_pwe() local
1213 if (!hwmgr || !hwmgr->pm_en) in pp_notify_smu_enable_pwe()
1216 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { in pp_notify_smu_enable_pwe()
1221 mutex_lock(&hwmgr->smu_lock); in pp_notify_smu_enable_pwe()
1222 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); in pp_notify_smu_enable_pwe()
1223 mutex_unlock(&hwmgr->smu_lock); in pp_notify_smu_enable_pwe()