Lines Matching refs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
227 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
228 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
237 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
440 uint8_t h_border;
441 uint8_t v_border;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
483 uint8_t mem_module_id;
484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
485 uint8_t reserved1[2];
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
547 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
548 uint8_t pwr_on_de_to_vary_bl;
549 uint8_t pwr_down_vary_bloff_to_de;
550 uint8_t pwr_down_de_to_digoff;
551 uint8_t pwr_off_delay;
552 uint8_t pwr_on_vary_bl_to_blon;
553 uint8_t pwr_down_bloff_to_vary_bloff;
554 uint8_t panel_bpc;
555 uint8_t dpcd_edp_config_cap;
556 uint8_t dpcd_max_link_rate;
557 uint8_t dpcd_max_lane_count;
558 uint8_t dpcd_max_downspread;
559 uint8_t min_allowed_bl_level;
560 uint8_t max_allowed_bl_level;
561 uint8_t bootup_bl_level;
562 uint8_t dplvdsrxid;
589 uint8_t gpio_bitshift;
590 uint8_t gpio_mask_bitshift;
591 uint8_t gpio_id;
592 uint8_t reserved;
663 uint8_t record_type; //An emun to indicate the record type
664 uint8_t record_size; //The size of the whole record in byte
670 uint8_t i2c_id;
671 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
677 …uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info …
678 uint8_t plugin_pin_state;
712 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
713 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
719 uint8_t flag; // Future expnadibility
720 uint8_t number_of_pins; // Number of GPIO pins used to control the object
758 uint8_t hpd_pin_map[8];
764 uint8_t aux_ddc_map[8];
771 uint8_t maxtmdsclkrate_in2_5mhz;
772 uint8_t reserved;
778 uint8_t connector_type;
779 uint8_t position;
795 uint8_t bracketlen;
796 uint8_t bracketwidth;
797 uint8_t conn_num;
798 uint8_t reserved;
822 uint8_t priority_id;
823 uint8_t reserved;
830 uint8_t number_of_path;
831 uint8_t reserved;
854 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
855 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
856 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
857 uint8_t ss_reserved;
858 …uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable wh…
859 uint8_t reserved1[3];
862 uint8_t dceip_min_ver;
863 uint8_t dceip_max_ver;
864 uint8_t max_disp_pipe_num;
865 uint8_t max_vbios_active_disp_pipe_num;
866 uint8_t max_ppll_num;
867 uint8_t max_disp_phy_num;
868 uint8_t max_aux_pairs;
869 uint8_t remotedisplayconfig;
870 uint8_t reserved3[8];
887 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
888 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
889 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
890 uint8_t ss_reserved;
891 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
892 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
893 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
894 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
897 uint8_t dcnip_min_ver;
898 uint8_t dcnip_max_ver;
899 uint8_t max_disp_pipe_num;
900 uint8_t max_vbios_active_disp_pipe_num;
901 uint8_t max_ppll_num;
902 uint8_t max_disp_phy_num;
903 uint8_t max_aux_pairs;
904 uint8_t remotedisplayconfig;
905 uint8_t reserved3[8];
930 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
931 uint8_t hpdlut_index; //An index into external HPD pin LUT
933 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
934 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
950 …uint8_t guid[16]; // a GUID is a 16 byte long st…
952 …uint8_t checksum; // a simple Checksum of the su…
953 uint8_t stereopinid; // use for eDP panel
954 uint8_t remotedisplayconfig;
955 uint8_t edptolvdsrxid;
956 …uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate …
957 uint8_t reserved[3]; // for potential expansion
968 uint8_t profile_id; // SENSOR_PROFILES
979 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
980 uint8_t module_name[8];
986 uint8_t flashlight_id; // 0: Rear, 1: Front
987 uint8_t name[8];
1003 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1004 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1006 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1007 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1008 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1009 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1013 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1015 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1016 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1020 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1021 uint8_t version;
1036 uint8_t sym_clk;
1037 uint8_t dig_mode;
1038 uint8_t phy_sel;
1040 uint8_t common_seldeemph60__deemph_6db_4_val;
1041 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1042 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1043 uint8_t margin_deemph_lane0__deemph_sel_val;
1047 uint8_t ucI2cRegIndex;
1048 uint8_t ucI2cRegVal;
1052 uint8_t HdmiSlvAddr;
1053 uint8_t HdmiRegNum;
1054 uint8_t Hdmi6GRegNum;
1077 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1078 uint8_t umachannelnumber; // number of memory channels
1079 …uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1080 uint8_t pwr_on_de_to_vary_bl;
1081 uint8_t pwr_down_vary_bloff_to_de;
1082 uint8_t pwr_down_de_to_digoff;
1083 uint8_t pwr_off_delay;
1084 uint8_t pwr_on_vary_bl_to_blon;
1085 uint8_t pwr_down_bloff_to_vary_bloff;
1086 uint8_t min_allowed_bl_level;
1087 uint8_t htc_hyst_limit;
1088 uint8_t htc_tmp_limit;
1089 uint8_t reserved1;
1090 uint8_t reserved2;
1187 uint8_t gfxip_min_ver;
1188 uint8_t gfxip_max_ver;
1189 uint8_t max_shader_engines;
1190 uint8_t max_tile_pipes;
1191 uint8_t max_cu_per_sh;
1192 uint8_t max_sh_per_se;
1193 uint8_t max_backends_per_se;
1194 uint8_t max_texture_channel_caches;
1207 uint8_t gfxip_min_ver;
1208 uint8_t gfxip_max_ver;
1209 uint8_t max_shader_engines;
1210 uint8_t max_tile_pipes;
1211 uint8_t max_cu_per_sh;
1212 uint8_t max_sh_per_se;
1213 uint8_t max_backends_per_se;
1214 uint8_t max_texture_channel_caches;
1223 uint8_t active_cu_per_sh;
1224 uint8_t active_rb_per_se;
1231 uint8_t gfxip_min_ver;
1232 uint8_t gfxip_max_ver;
1233 uint8_t gc_num_se;
1234 uint8_t max_tile_pipes;
1235 uint8_t gc_num_cu_per_sh;
1236 uint8_t gc_num_sh_per_se;
1237 uint8_t gc_num_rb_per_se;
1238 uint8_t gc_num_tccs;
1247 uint8_t active_cu_per_sh;
1248 uint8_t active_rb_per_se;
1256 uint8_t gc_num_max_gs_thds;
1257 uint8_t gc_gs_table_depth;
1258 uint8_t gc_double_offchip_lds_buffer;
1259 uint8_t gc_max_scratch_slots_per_cu;
1272 uint8_t smuip_min_ver;
1273 uint8_t smuip_max_ver;
1274 uint8_t smu_rsd1;
1275 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1281 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1282 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1283 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1284 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1285 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1286 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1287 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1288 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1293 uint8_t smuip_min_ver;
1294 uint8_t smuip_max_ver;
1295 uint8_t smu_rsd1;
1296 uint8_t gpuclk_ss_mode;
1302 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1303 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1304 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1305 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1306 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1307 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1308 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1309 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1310 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1311 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1326 uint8_t smuip_min_ver;
1327 uint8_t smuip_max_ver;
1328 uint8_t smu_rsd1;
1329 uint8_t gpuclk_ss_mode;
1335 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1336 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1337 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1338 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1339 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1340 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1341 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1342 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1343 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1344 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1369 uint8_t liquid1_i2c_address;
1370 uint8_t liquid2_i2c_address;
1371 uint8_t vr_i2c_address;
1372 uint8_t plx_i2c_address;
1374 uint8_t liquid_i2c_linescl;
1375 uint8_t liquid_i2c_linesda;
1376 uint8_t vr_i2c_linescl;
1377 uint8_t vr_i2c_linesda;
1379 uint8_t plx_i2c_linescl;
1380 uint8_t plx_i2c_linesda;
1381 uint8_t vrsensorpresent;
1382 uint8_t liquidsensorpresent;
1387 uint8_t vddgfxvrmapping;
1388 uint8_t vddsocvrmapping;
1389 uint8_t vddmem0vrmapping;
1390 uint8_t vddmem1vrmapping;
1392 uint8_t gfxulvphasesheddingmask;
1393 uint8_t soculvphasesheddingmask;
1394 uint8_t padding8_v[2];
1397 uint8_t gfxoffset;
1398 uint8_t padding_telemetrygfx;
1401 uint8_t socoffset;
1402 uint8_t padding_telemetrysoc;
1405 uint8_t mem0offset;
1406 uint8_t padding_telemetrymem0;
1409 uint8_t mem1offset;
1410 uint8_t padding_telemetrymem1;
1412 uint8_t acdcgpio;
1413 uint8_t acdcpolarity;
1414 uint8_t vr0hotgpio;
1415 uint8_t vr0hotpolarity;
1417 uint8_t vr1hotgpio;
1418 uint8_t vr1hotpolarity;
1419 uint8_t padding1;
1420 uint8_t padding2;
1422 uint8_t ledpin0;
1423 uint8_t ledpin1;
1424 uint8_t ledpin2;
1425 uint8_t padding8_4;
1427 uint8_t pllgfxclkspreadenabled;
1428 uint8_t pllgfxclkspreadpercent;
1431 uint8_t uclkspreadenabled;
1432 uint8_t uclkspreadpercent;
1435 uint8_t socclkspreadenabled;
1436 uint8_t socclkspreadpercent;
1439 uint8_t acggfxclkspreadenabled;
1440 uint8_t acggfxclkspreadpercent;
1443 uint8_t Vr2_I2C_address;
1444 uint8_t padding_vr2[3];
1478 uint8_t enable_gb_vdroop_table_cksoff;
1479 uint8_t enable_gb_vdroop_table_ckson;
1480 uint8_t enable_gb_fuse_table_cksoff;
1481 uint8_t enable_gb_fuse_table_ckson;
1483 uint8_t enable_apply_avfs_cksoff_voltage;
1484 uint8_t reserved;
1522 uint8_t enable_gb_vdroop_table_cksoff;
1523 uint8_t enable_gb_vdroop_table_ckson;
1524 uint8_t enable_gb_fuse_table_cksoff;
1525 uint8_t enable_gb_fuse_table_ckson;
1527 uint8_t enable_apply_avfs_cksoff_voltage;
1528 uint8_t reserved;
1547 uint8_t enable_acg_gb_vdroop_table;
1548 uint8_t enable_acg_gb_fuse_table;
1571 uint8_t uvdip_min_ver;
1572 uint8_t uvdip_max_ver;
1573 uint8_t vceip_min_ver;
1574 uint8_t vceip_max_ver;
1599 uint8_t umcip_min_ver;
1600 uint8_t umcip_max_ver;
1601 uint8_t vram_type; //enum of atom_dgpu_vram_type
1602 uint8_t umc_config;
1621 uint8_t ext_memory_id; // Current memory module ID
1622 uint8_t memory_type; // enum of atom_dgpu_vram_type
1623 uint8_t channel_num; // Number of mem. channels supported in this module
1624 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1625 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1626 uint8_t tunningset_id; // MC phy registers set per.
1627 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
1628 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1643 uint8_t vram_module_num; // indicate number of VRAM module
1644 uint8_t vram_rsd1[2];
1645 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
1702 uint8_t voltage_type; //enum atom_voltage_type
1703 uint8_t voltage_mode; //enum atom_voltage_object_mode
1721 uint8_t regulator_id; //Indicate Voltage Regulator Id
1722 uint8_t i2c_id;
1723 uint8_t i2c_slave_addr;
1724 uint8_t i2c_control_offset;
1725 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
1726 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
1727 uint8_t reserved[2];
1748 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
1749 …uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value L…
1750 uint8_t phase_delay_us; // phase delay in unit of micro second
1751 uint8_t reserved;
1759 …uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and…
1760 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
1761 uint8_t psi0_enable; //
1762 uint8_t maxvstep;
1763 uint8_t telemetry_offset;
1764 uint8_t telemetry_gain;
1771 uint8_t merged_powerrail_type; //enum atom_voltage_type
1772 uint8_t reserved[3];
1917 uint8_t voltagetype; /* enum atom_voltage_type */
1918 …uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_…
1966 uint8_t pll_ss_enable;
1967 uint8_t reserved;
1982 uint8_t reserved;
1983 uint8_t bitslen;
2001 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
2002 …uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLO…
2003 uint8_t command; // enum of atom_get_smu_clock_info_command
2004 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
2141 uint8_t ucode_func_id;
2142 uint8_t ucode_reserved[3];
2157 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2158 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2160 uint8_t encoder_mode; // Encoder mode:
2161 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2162 uint8_t crtc_id; // enum of atom_crtc_def
2163 …uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepc…
2164 uint8_t reserved1[2];
2203 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2204 …uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK …
2205 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
2206 …uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use on…
2250 uint8_t crtc_id; // enum atom_crtc_def
2251 uint8_t blanking; // enum atom_blank_crtc_command
2267 uint8_t crtc_id; // enum atom_crtc_def
2268 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2269 uint8_t padding[2];
2278 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2279 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2280 uint8_t padding[2];
2303 uint8_t h_border;
2304 uint8_t v_border;
2305 uint8_t crtc_id; // enum atom_crtc_def
2306 uint8_t encoder_mode; // atom_encode_mode_def
2307 uint8_t padding[2];
2316 uint8_t i2cspeed_khz;
2318 uint8_t regindex;
2319 uint8_t status; /* enum atom_process_i2c_flag */
2322 uint8_t flag; /* enum atom_process_i2c_status */
2323 uint8_t trans_bytes;
2324 uint8_t slave_addr;
2325 uint8_t i2c_id;
2353 uint8_t channelid;
2355 uint8_t reply_status;
2356 uint8_t aux_delay;
2358 uint8_t dataout_len;
2359 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
2369 uint8_t crtc_id; // enum atom_crtc_def
2370 uint8_t encoder_id; // enum atom_dig_def
2371 uint8_t encode_mode; // enum atom_encode_mode_def
2372 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2422 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2423 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2424 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2425 uint8_t lanenum; // Lane number
2427 uint8_t bitpercolor;
2428 …uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz…
2429 uint8_t reserved[2];
2434 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2435 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2436 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2437 uint8_t lanenum; // Lane number
2438 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2439 uint8_t hpd_sel;
2440 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2441 uint8_t reserved[2];
2446 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2447 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2448 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2449 uint8_t reserved1;
2455 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2456 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2457 uint8_t reserved1[2];
2476 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2477 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
2479 uint8_t digmode; // enum atom_encode_mode_def
2480 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
2482 uint8_t lanenum; // Lane number 1, 2, 4, 8
2484 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2485 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2486 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
2487 uint8_t reserved;
2565 …uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENAB…
2566 uint8_t action; //
2567 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2568 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2569 …uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPU…
2570 uint8_t hpd_id;
2618 uint8_t revision;
2619 uint8_t checksum;
2620 uint8_t oemId[6];
2621 uint8_t oemTableId[8]; //UINT64 OemTableId;
2629 uint8_t tableUUID[16]; //0x24
2650 uint8_t vbioscontent[1];
2655 uint8_t lib1content[1];