244 		cntl->bitfields.mask =  in dbgdev_address_watch_set_registers()
248 		cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;  in dbgdev_address_watch_set_registers()
252 	addrHi->bitfields.addr = addr.u.high_part &  in dbgdev_address_watch_set_registers()
254 	addrLo->bitfields.addr =  in dbgdev_address_watch_set_registers()
257 	cntl->bitfields.mode = adw_info->watch_mode[index];  in dbgdev_address_watch_set_registers()
258 	cntl->bitfields.vmid = (uint32_t) vmid;  in dbgdev_address_watch_set_registers()
262 	pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);  in dbgdev_address_watch_set_registers()
264 			addrHi->bitfields.addr);  in dbgdev_address_watch_set_registers()
266 			addrLo->bitfields.addr);  in dbgdev_address_watch_set_registers()
309 				addrLo.bitfields.addr);  in dbgdev_address_watch_nodiq()
311 				addrHi.bitfields.addr);  in dbgdev_address_watch_nodiq()
313 				addrHi.bitfields.addr);  in dbgdev_address_watch_nodiq()
315 				cntl.bitfields.mask);  in dbgdev_address_watch_nodiq()
317 				cntl.bitfields.mode);  in dbgdev_address_watch_nodiq()
319 				cntl.bitfields.vmid);  in dbgdev_address_watch_nodiq()
321 				cntl.bitfields.atc);  in dbgdev_address_watch_nodiq()
408 				addrLo.bitfields.addr);  in dbgdev_address_watch_diq()
410 				addrHi.bitfields.addr);  in dbgdev_address_watch_diq()
412 				cntl.bitfields.mask);  in dbgdev_address_watch_diq()
414 				cntl.bitfields.mode);  in dbgdev_address_watch_diq()
416 				cntl.bitfields.vmid);  in dbgdev_address_watch_diq()
418 				cntl.bitfields.atc);  in dbgdev_address_watch_diq()
454 			cntl.bitfields.valid = 1;  in dbgdev_address_watch_diq()
456 			cntl.bitfields.valid = 0;  in dbgdev_address_watch_diq()
616 	pr_debug("\t\t chk_vmid  is : %u\n", reg_sq_cmd.bitfields.check_vmid);  in dbgdev_wave_control_diq()
617 	pr_debug("\t\t command   is : %u\n", reg_sq_cmd.bitfields.cmd);  in dbgdev_wave_control_diq()
618 	pr_debug("\t\t queue id  is : %u\n", reg_sq_cmd.bitfields.queue_id);  in dbgdev_wave_control_diq()
619 	pr_debug("\t\t simd id   is : %u\n", reg_sq_cmd.bitfields.simd_id);  in dbgdev_wave_control_diq()
620 	pr_debug("\t\t mode      is : %u\n", reg_sq_cmd.bitfields.mode);  in dbgdev_wave_control_diq()
621 	pr_debug("\t\t vm_id     is : %u\n", reg_sq_cmd.bitfields.vm_id);  in dbgdev_wave_control_diq()
622 	pr_debug("\t\t wave_id   is : %u\n", reg_sq_cmd.bitfields.wave_id);  in dbgdev_wave_control_diq()
625 			reg_gfx_index.bitfields.instance_broadcast_writes);  in dbgdev_wave_control_diq()
627 			reg_gfx_index.bitfields.instance_index);  in dbgdev_wave_control_diq()
629 			reg_gfx_index.bitfields.se_broadcast_writes);  in dbgdev_wave_control_diq()
630 	pr_debug("\t\t se_ind    is : %u\n", reg_gfx_index.bitfields.se_index);  in dbgdev_wave_control_diq()
631 	pr_debug("\t\t sh_ind    is : %u\n", reg_gfx_index.bitfields.sh_index);  in dbgdev_wave_control_diq()
633 			reg_gfx_index.bitfields.sh_broadcast_writes);  in dbgdev_wave_control_diq()
734 	pr_debug("\t\t chk_vmid  is : %u\n", reg_sq_cmd.bitfields.check_vmid);  in dbgdev_wave_control_nodiq()
735 	pr_debug("\t\t command   is : %u\n", reg_sq_cmd.bitfields.cmd);  in dbgdev_wave_control_nodiq()
736 	pr_debug("\t\t queue id  is : %u\n", reg_sq_cmd.bitfields.queue_id);  in dbgdev_wave_control_nodiq()
737 	pr_debug("\t\t simd id   is : %u\n", reg_sq_cmd.bitfields.simd_id);  in dbgdev_wave_control_nodiq()
738 	pr_debug("\t\t mode      is : %u\n", reg_sq_cmd.bitfields.mode);  in dbgdev_wave_control_nodiq()
739 	pr_debug("\t\t vm_id     is : %u\n", reg_sq_cmd.bitfields.vm_id);  in dbgdev_wave_control_nodiq()
740 	pr_debug("\t\t wave_id   is : %u\n", reg_sq_cmd.bitfields.wave_id);  in dbgdev_wave_control_nodiq()
743 			reg_gfx_index.bitfields.instance_broadcast_writes);  in dbgdev_wave_control_nodiq()
745 			reg_gfx_index.bitfields.instance_index);  in dbgdev_wave_control_nodiq()
747 			reg_gfx_index.bitfields.se_broadcast_writes);  in dbgdev_wave_control_nodiq()
748 	pr_debug("\t\t se_ind    is : %u\n", reg_gfx_index.bitfields.se_index);  in dbgdev_wave_control_nodiq()
749 	pr_debug("\t\t sh_ind    is : %u\n", reg_gfx_index.bitfields.sh_index);  in dbgdev_wave_control_nodiq()
751 			reg_gfx_index.bitfields.sh_broadcast_writes);  in dbgdev_wave_control_nodiq()