52 	adev->irq.ih.enabled = true;  in vega10_ih_enable_interrupts()
72 	adev->irq.ih.enabled = false;  in vega10_ih_disable_interrupts()
73 	adev->irq.ih.rptr = 0;  in vega10_ih_disable_interrupts()
102 	if (adev->irq.ih.use_bus_addr) {  in vega10_ih_irq_init()
103 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);  in vega10_ih_irq_init()
104 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);  in vega10_ih_irq_init()
107 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in vega10_ih_irq_init()
108 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);  in vega10_ih_irq_init()
111 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in vega10_ih_irq_init()
127 	if (adev->irq.ih.use_bus_addr)  in vega10_ih_irq_init()
128 		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);  in vega10_ih_irq_init()
130 		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);  in vega10_ih_irq_init()
139 	if (adev->irq.ih.use_doorbell) {  in vega10_ih_irq_init()
141 						 OFFSET, adev->irq.ih.doorbell_index);  in vega10_ih_irq_init()
149 	adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,  in vega10_ih_irq_init()
150 					    adev->irq.ih.doorbell_index);  in vega10_ih_irq_init()
198 	if (adev->irq.ih.use_bus_addr)  in vega10_ih_get_wptr()
199 		wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);  in vega10_ih_get_wptr()
201 		wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);  in vega10_ih_get_wptr()
210 		tmp = (wptr + 32) & adev->irq.ih.ptr_mask;  in vega10_ih_get_wptr()
212 			wptr, adev->irq.ih.rptr, tmp);  in vega10_ih_get_wptr()
213 		adev->irq.ih.rptr = tmp;  in vega10_ih_get_wptr()
219 	return (wptr & adev->irq.ih.ptr_mask);  in vega10_ih_get_wptr()
231 	u32 ring_index = adev->irq.ih.rptr >> 2;  in vega10_ih_prescreen_iv()
238 	dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);  in vega10_ih_prescreen_iv()
239 	dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);  in vega10_ih_prescreen_iv()
240 	dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);  in vega10_ih_prescreen_iv()
241 	dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);  in vega10_ih_prescreen_iv()
301 	adev->irq.ih.rptr += 32;  in vega10_ih_prescreen_iv()
317 	u32 ring_index = adev->irq.ih.rptr >> 2;  in vega10_ih_decode_iv()
320 	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);  in vega10_ih_decode_iv()
321 	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);  in vega10_ih_decode_iv()
322 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);  in vega10_ih_decode_iv()
323 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);  in vega10_ih_decode_iv()
324 	dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);  in vega10_ih_decode_iv()
325 	dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);  in vega10_ih_decode_iv()
326 	dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]);  in vega10_ih_decode_iv()
327 	dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]);  in vega10_ih_decode_iv()
345 	adev->irq.ih.rptr += 32;  in vega10_ih_decode_iv()
357 	if (adev->irq.ih.use_doorbell) {  in vega10_ih_set_rptr()
359 		if (adev->irq.ih.use_bus_addr)  in vega10_ih_set_rptr()
360 			adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;  in vega10_ih_set_rptr()
362 			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;  in vega10_ih_set_rptr()
363 		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);  in vega10_ih_set_rptr()
365 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);  in vega10_ih_set_rptr()
386 	adev->irq.ih.use_doorbell = true;  in vega10_ih_sw_init()
387 	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;  in vega10_ih_sw_init()
389 	adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL);  in vega10_ih_sw_init()
390 	if (!adev->irq.ih.faults)  in vega10_ih_sw_init()
392 	INIT_CHASH_TABLE(adev->irq.ih.faults->hash,  in vega10_ih_sw_init()
394 	spin_lock_init(&adev->irq.ih.faults->lock);  in vega10_ih_sw_init()
395 	adev->irq.ih.faults->count = 0;  in vega10_ih_sw_init()
409 	kfree(adev->irq.ih.faults);  in vega10_ih_sw_fini()
410 	adev->irq.ih.faults = NULL;  in vega10_ih_sw_fini()