45 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
77 	struct amdgpu_ring *ring;  in vcn_v1_0_sw_init()  local
117 	ring = &adev->vcn.ring_dec;  in vcn_v1_0_sw_init()
118 	sprintf(ring->name, "vcn_dec");  in vcn_v1_0_sw_init()
119 	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);  in vcn_v1_0_sw_init()
124 		ring = &adev->vcn.ring_enc[i];  in vcn_v1_0_sw_init()
125 		sprintf(ring->name, "vcn_enc%d", i);  in vcn_v1_0_sw_init()
126 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);  in vcn_v1_0_sw_init()
131 	ring = &adev->vcn.ring_jpeg;  in vcn_v1_0_sw_init()
132 	sprintf(ring->name, "vcn_jpeg");  in vcn_v1_0_sw_init()
133 	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);  in vcn_v1_0_sw_init()
171 	struct amdgpu_ring *ring = &adev->vcn.ring_dec;  in vcn_v1_0_hw_init()  local
174 	ring->ready = true;  in vcn_v1_0_hw_init()
175 	r = amdgpu_ring_test_ring(ring);  in vcn_v1_0_hw_init()
177 		ring->ready = false;  in vcn_v1_0_hw_init()
182 		ring = &adev->vcn.ring_enc[i];  in vcn_v1_0_hw_init()
183 		ring->ready = true;  in vcn_v1_0_hw_init()
184 		r = amdgpu_ring_test_ring(ring);  in vcn_v1_0_hw_init()
186 			ring->ready = false;  in vcn_v1_0_hw_init()
191 	ring = &adev->vcn.ring_jpeg;  in vcn_v1_0_hw_init()
192 	ring->ready = true;  in vcn_v1_0_hw_init()
193 	r = amdgpu_ring_test_ring(ring);  in vcn_v1_0_hw_init()
195 		ring->ready = false;  in vcn_v1_0_hw_init()
216 	struct amdgpu_ring *ring = &adev->vcn.ring_dec;  in vcn_v1_0_hw_fini()  local
221 	ring->ready = false;  in vcn_v1_0_hw_fini()
619 	struct amdgpu_ring *ring = &adev->vcn.ring_dec;  in vcn_v1_0_start()  local
732 	rb_bufsz = order_base_2(ring->ring_size);  in vcn_v1_0_start()
746 			(upper_32_bits(ring->gpu_addr) >> 2));  in vcn_v1_0_start()
750 			lower_32_bits(ring->gpu_addr));  in vcn_v1_0_start()
752 			upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start()
757 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);  in vcn_v1_0_start()
759 			lower_32_bits(ring->wptr));  in vcn_v1_0_start()
764 	ring = &adev->vcn.ring_enc[0];  in vcn_v1_0_start()
765 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v1_0_start()
766 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v1_0_start()
767 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v1_0_start()
768 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start()
769 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v1_0_start()
771 	ring = &adev->vcn.ring_enc[1];  in vcn_v1_0_start()
772 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v1_0_start()
773 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v1_0_start()
774 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v1_0_start()
775 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start()
776 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v1_0_start()
778 	ring = &adev->vcn.ring_jpeg;  in vcn_v1_0_start()
781 	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));  in vcn_v1_0_start()
782 	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_start()
788 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);  in vcn_v1_0_start()
791 	vcn_v1_0_jpeg_ring_set_patch_ring(ring,  in vcn_v1_0_start()
792 		(ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));  in vcn_v1_0_start()
876 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)  in vcn_v1_0_dec_ring_get_rptr()  argument
878 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_get_rptr()
890 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)  in vcn_v1_0_dec_ring_get_wptr()  argument
892 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_get_wptr()
904 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)  in vcn_v1_0_dec_ring_set_wptr()  argument
906 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_set_wptr()
908 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v1_0_dec_ring_set_wptr()
918 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)  in vcn_v1_0_dec_ring_insert_start()  argument
920 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_insert_start()
922 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_insert_start()
924 	amdgpu_ring_write(ring, 0);  in vcn_v1_0_dec_ring_insert_start()
925 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_insert_start()
927 	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);  in vcn_v1_0_dec_ring_insert_start()
937 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)  in vcn_v1_0_dec_ring_insert_end()  argument
939 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_insert_end()
941 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_insert_end()
943 	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);  in vcn_v1_0_dec_ring_insert_end()
954 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,  in vcn_v1_0_dec_ring_emit_fence()  argument
957 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_emit_fence()
961 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
963 	amdgpu_ring_write(ring, seq);  in vcn_v1_0_dec_ring_emit_fence()
964 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
966 	amdgpu_ring_write(ring, addr & 0xffffffff);  in vcn_v1_0_dec_ring_emit_fence()
967 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
969 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);  in vcn_v1_0_dec_ring_emit_fence()
970 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
972 	amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);  in vcn_v1_0_dec_ring_emit_fence()
974 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
976 	amdgpu_ring_write(ring, 0);  in vcn_v1_0_dec_ring_emit_fence()
977 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
979 	amdgpu_ring_write(ring, 0);  in vcn_v1_0_dec_ring_emit_fence()
980 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_fence()
982 	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);  in vcn_v1_0_dec_ring_emit_fence()
993 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,  in vcn_v1_0_dec_ring_emit_ib()  argument
997 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_emit_ib()
999 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_ib()
1001 	amdgpu_ring_write(ring, vmid);  in vcn_v1_0_dec_ring_emit_ib()
1003 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_ib()
1005 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in vcn_v1_0_dec_ring_emit_ib()
1006 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_ib()
1008 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in vcn_v1_0_dec_ring_emit_ib()
1009 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_ib()
1011 	amdgpu_ring_write(ring, ib->length_dw);  in vcn_v1_0_dec_ring_emit_ib()
1014 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,  in vcn_v1_0_dec_ring_emit_reg_wait()  argument
1018 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_emit_reg_wait()
1020 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_reg_wait()
1022 	amdgpu_ring_write(ring, reg << 2);  in vcn_v1_0_dec_ring_emit_reg_wait()
1023 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_reg_wait()
1025 	amdgpu_ring_write(ring, val);  in vcn_v1_0_dec_ring_emit_reg_wait()
1026 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_reg_wait()
1028 	amdgpu_ring_write(ring, mask);  in vcn_v1_0_dec_ring_emit_reg_wait()
1029 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_reg_wait()
1031 	amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);  in vcn_v1_0_dec_ring_emit_reg_wait()
1034 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,  in vcn_v1_0_dec_ring_emit_vm_flush()  argument
1037 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];  in vcn_v1_0_dec_ring_emit_vm_flush()
1040 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);  in vcn_v1_0_dec_ring_emit_vm_flush()
1046 	vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);  in vcn_v1_0_dec_ring_emit_vm_flush()
1049 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,  in vcn_v1_0_dec_ring_emit_wreg()  argument
1052 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_emit_wreg()
1054 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_wreg()
1056 	amdgpu_ring_write(ring, reg << 2);  in vcn_v1_0_dec_ring_emit_wreg()
1057 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_wreg()
1059 	amdgpu_ring_write(ring, val);  in vcn_v1_0_dec_ring_emit_wreg()
1060 	amdgpu_ring_write(ring,  in vcn_v1_0_dec_ring_emit_wreg()
1062 	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);  in vcn_v1_0_dec_ring_emit_wreg()
1072 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)  in vcn_v1_0_enc_ring_get_rptr()  argument
1074 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_enc_ring_get_rptr()
1076 	if (ring == &adev->vcn.ring_enc[0])  in vcn_v1_0_enc_ring_get_rptr()
1089 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)  in vcn_v1_0_enc_ring_get_wptr()  argument
1091 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_enc_ring_get_wptr()
1093 	if (ring == &adev->vcn.ring_enc[0])  in vcn_v1_0_enc_ring_get_wptr()
1106 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)  in vcn_v1_0_enc_ring_set_wptr()  argument
1108 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_enc_ring_set_wptr()
1110 	if (ring == &adev->vcn.ring_enc[0])  in vcn_v1_0_enc_ring_set_wptr()
1112 			lower_32_bits(ring->wptr));  in vcn_v1_0_enc_ring_set_wptr()
1115 			lower_32_bits(ring->wptr));  in vcn_v1_0_enc_ring_set_wptr()
1126 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,  in vcn_v1_0_enc_ring_emit_fence()  argument
1131 	amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);  in vcn_v1_0_enc_ring_emit_fence()
1132 	amdgpu_ring_write(ring, addr);  in vcn_v1_0_enc_ring_emit_fence()
1133 	amdgpu_ring_write(ring, upper_32_bits(addr));  in vcn_v1_0_enc_ring_emit_fence()
1134 	amdgpu_ring_write(ring, seq);  in vcn_v1_0_enc_ring_emit_fence()
1135 	amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);  in vcn_v1_0_enc_ring_emit_fence()
1138 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)  in vcn_v1_0_enc_ring_insert_end()  argument
1140 	amdgpu_ring_write(ring, VCN_ENC_CMD_END);  in vcn_v1_0_enc_ring_insert_end()
1151 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,  in vcn_v1_0_enc_ring_emit_ib()  argument
1154 	amdgpu_ring_write(ring, VCN_ENC_CMD_IB);  in vcn_v1_0_enc_ring_emit_ib()
1155 	amdgpu_ring_write(ring, vmid);  in vcn_v1_0_enc_ring_emit_ib()
1156 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in vcn_v1_0_enc_ring_emit_ib()
1157 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in vcn_v1_0_enc_ring_emit_ib()
1158 	amdgpu_ring_write(ring, ib->length_dw);  in vcn_v1_0_enc_ring_emit_ib()
1161 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,  in vcn_v1_0_enc_ring_emit_reg_wait()  argument
1165 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);  in vcn_v1_0_enc_ring_emit_reg_wait()
1166 	amdgpu_ring_write(ring, reg << 2);  in vcn_v1_0_enc_ring_emit_reg_wait()
1167 	amdgpu_ring_write(ring, mask);  in vcn_v1_0_enc_ring_emit_reg_wait()
1168 	amdgpu_ring_write(ring, val);  in vcn_v1_0_enc_ring_emit_reg_wait()
1171 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,  in vcn_v1_0_enc_ring_emit_vm_flush()  argument
1174 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];  in vcn_v1_0_enc_ring_emit_vm_flush()
1176 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);  in vcn_v1_0_enc_ring_emit_vm_flush()
1179 	vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,  in vcn_v1_0_enc_ring_emit_vm_flush()
1183 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,  in vcn_v1_0_enc_ring_emit_wreg()  argument
1186 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);  in vcn_v1_0_enc_ring_emit_wreg()
1187 	amdgpu_ring_write(ring,	reg << 2);  in vcn_v1_0_enc_ring_emit_wreg()
1188 	amdgpu_ring_write(ring, val);  in vcn_v1_0_enc_ring_emit_wreg()
1199 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)  in vcn_v1_0_jpeg_ring_get_rptr()  argument
1201 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_get_rptr()
1213 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)  in vcn_v1_0_jpeg_ring_get_wptr()  argument
1215 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_get_wptr()
1227 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)  in vcn_v1_0_jpeg_ring_set_wptr()  argument
1229 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_set_wptr()
1231 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v1_0_jpeg_ring_set_wptr()
1241 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)  in vcn_v1_0_jpeg_ring_insert_start()  argument
1243 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_insert_start()
1245 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_insert_start()
1247 	amdgpu_ring_write(ring, 0x68e04);  in vcn_v1_0_jpeg_ring_insert_start()
1249 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));  in vcn_v1_0_jpeg_ring_insert_start()
1250 	amdgpu_ring_write(ring, 0x80010000);  in vcn_v1_0_jpeg_ring_insert_start()
1260 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)  in vcn_v1_0_jpeg_ring_insert_end()  argument
1262 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_insert_end()
1264 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_insert_end()
1266 	amdgpu_ring_write(ring, 0x68e04);  in vcn_v1_0_jpeg_ring_insert_end()
1268 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));  in vcn_v1_0_jpeg_ring_insert_end()
1269 	amdgpu_ring_write(ring, 0x00010000);  in vcn_v1_0_jpeg_ring_insert_end()
1280 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,  in vcn_v1_0_jpeg_ring_emit_fence()  argument
1283 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_emit_fence()
1287 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1289 	amdgpu_ring_write(ring, seq);  in vcn_v1_0_jpeg_ring_emit_fence()
1291 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1293 	amdgpu_ring_write(ring, seq);  in vcn_v1_0_jpeg_ring_emit_fence()
1295 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1297 	amdgpu_ring_write(ring, lower_32_bits(addr));  in vcn_v1_0_jpeg_ring_emit_fence()
1299 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1301 	amdgpu_ring_write(ring, upper_32_bits(addr));  in vcn_v1_0_jpeg_ring_emit_fence()
1303 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1305 	amdgpu_ring_write(ring, 0x8);  in vcn_v1_0_jpeg_ring_emit_fence()
1307 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1309 	amdgpu_ring_write(ring, 0);  in vcn_v1_0_jpeg_ring_emit_fence()
1311 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1313 	amdgpu_ring_write(ring, 0x01400200);  in vcn_v1_0_jpeg_ring_emit_fence()
1315 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1317 	amdgpu_ring_write(ring, seq);  in vcn_v1_0_jpeg_ring_emit_fence()
1319 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1321 	amdgpu_ring_write(ring, lower_32_bits(addr));  in vcn_v1_0_jpeg_ring_emit_fence()
1323 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1325 	amdgpu_ring_write(ring, upper_32_bits(addr));  in vcn_v1_0_jpeg_ring_emit_fence()
1327 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1329 	amdgpu_ring_write(ring, 0xffffffff);  in vcn_v1_0_jpeg_ring_emit_fence()
1331 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1333 	amdgpu_ring_write(ring, 0x3fbc);  in vcn_v1_0_jpeg_ring_emit_fence()
1335 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_fence()
1337 	amdgpu_ring_write(ring, 0x1);  in vcn_v1_0_jpeg_ring_emit_fence()
1348 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,  in vcn_v1_0_jpeg_ring_emit_ib()  argument
1352 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_emit_ib()
1354 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1356 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));  in vcn_v1_0_jpeg_ring_emit_ib()
1358 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1360 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));  in vcn_v1_0_jpeg_ring_emit_ib()
1362 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1364 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in vcn_v1_0_jpeg_ring_emit_ib()
1366 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1368 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in vcn_v1_0_jpeg_ring_emit_ib()
1370 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1372 	amdgpu_ring_write(ring, ib->length_dw);  in vcn_v1_0_jpeg_ring_emit_ib()
1374 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1376 	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));  in vcn_v1_0_jpeg_ring_emit_ib()
1378 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1380 	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));  in vcn_v1_0_jpeg_ring_emit_ib()
1382 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1384 	amdgpu_ring_write(ring, 0);  in vcn_v1_0_jpeg_ring_emit_ib()
1386 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1388 	amdgpu_ring_write(ring, 0x01400200);  in vcn_v1_0_jpeg_ring_emit_ib()
1390 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1392 	amdgpu_ring_write(ring, 0x2);  in vcn_v1_0_jpeg_ring_emit_ib()
1394 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_ib()
1396 	amdgpu_ring_write(ring, 0x2);  in vcn_v1_0_jpeg_ring_emit_ib()
1399 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,  in vcn_v1_0_jpeg_ring_emit_reg_wait()  argument
1403 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1406 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1408 	amdgpu_ring_write(ring, 0x01400200);  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1410 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1412 	amdgpu_ring_write(ring, val);  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1414 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1418 		amdgpu_ring_write(ring, 0);  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1419 		amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1422 		amdgpu_ring_write(ring, reg_offset);  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1423 		amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1426 	amdgpu_ring_write(ring, mask);  in vcn_v1_0_jpeg_ring_emit_reg_wait()
1429 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,  in vcn_v1_0_jpeg_ring_emit_vm_flush()  argument
1432 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];  in vcn_v1_0_jpeg_ring_emit_vm_flush()
1435 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);  in vcn_v1_0_jpeg_ring_emit_vm_flush()
1441 	vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);  in vcn_v1_0_jpeg_ring_emit_vm_flush()
1444 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,  in vcn_v1_0_jpeg_ring_emit_wreg()  argument
1447 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_emit_wreg()
1450 	amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_wreg()
1454 		amdgpu_ring_write(ring, 0);  in vcn_v1_0_jpeg_ring_emit_wreg()
1455 		amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_wreg()
1458 		amdgpu_ring_write(ring, reg_offset);  in vcn_v1_0_jpeg_ring_emit_wreg()
1459 		amdgpu_ring_write(ring,  in vcn_v1_0_jpeg_ring_emit_wreg()
1462 	amdgpu_ring_write(ring, val);  in vcn_v1_0_jpeg_ring_emit_wreg()
1465 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)  in vcn_v1_0_jpeg_ring_nop()  argument
1469 	WARN_ON(ring->wptr % 2 || count % 2);  in vcn_v1_0_jpeg_ring_nop()
1472 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));  in vcn_v1_0_jpeg_ring_nop()
1473 		amdgpu_ring_write(ring, 0);  in vcn_v1_0_jpeg_ring_nop()
1477 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_off…  in vcn_v1_0_jpeg_ring_patch_wreg()  argument
1479 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_patch_wreg()
1480 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKE…  in vcn_v1_0_jpeg_ring_patch_wreg()
1483 		ring->ring[(*ptr)++] = 0;  in vcn_v1_0_jpeg_ring_patch_wreg()
1484 		ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);  in vcn_v1_0_jpeg_ring_patch_wreg()
1486 		ring->ring[(*ptr)++] = reg_offset;  in vcn_v1_0_jpeg_ring_patch_wreg()
1487 		ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);  in vcn_v1_0_jpeg_ring_patch_wreg()
1489 	ring->ring[(*ptr)++] = val;  in vcn_v1_0_jpeg_ring_patch_wreg()
1492 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)  in vcn_v1_0_jpeg_ring_set_patch_ring()  argument
1494 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1501 	val = lower_32_bits(ring->gpu_addr);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1502 	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1507 	val = upper_32_bits(ring->gpu_addr);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1508 	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1512 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1513 		ring->ring[ptr++] = 0;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1520 	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1526 	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1534 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_T…  in vcn_v1_0_jpeg_ring_set_patch_ring()
1535 	ring->ring[ptr++] = 0x01400200;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1536 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1537 	ring->ring[ptr++] = val;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1538 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_…  in vcn_v1_0_jpeg_ring_set_patch_ring()
1541 		ring->ring[ptr++] = 0;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1542 		ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1544 		ring->ring[ptr++] = reg_offset;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1545 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1547 	ring->ring[ptr++] = mask;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1551 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1552 		ring->ring[ptr++] = 0;  in vcn_v1_0_jpeg_ring_set_patch_ring()
1559 	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1565 	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);  in vcn_v1_0_jpeg_ring_set_patch_ring()
1604 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)  in vcn_v1_0_dec_ring_insert_nop()  argument
1606 	struct amdgpu_device *adev = ring->adev;  in vcn_v1_0_dec_ring_insert_nop()
1609 	WARN_ON(ring->wptr % 2 || count % 2);  in vcn_v1_0_dec_ring_insert_nop()
1612 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));  in vcn_v1_0_dec_ring_insert_nop()
1613 		amdgpu_ring_write(ring, 0);  in vcn_v1_0_dec_ring_insert_nop()