86 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_ring_get_rptr()
88 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_ring_get_rptr()
97 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_ring_get_rptr()
118 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_ring_get_wptr()
120 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_ring_get_wptr()
129 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_ring_get_wptr()
149 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_ring_set_wptr()
151 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_ring_set_wptr()
154 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v3_0_ring_set_wptr()
156 		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v3_0_ring_set_wptr()
158 		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));  in vce_v3_0_ring_set_wptr()
160 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_ring_set_wptr()
186 		WREG32(mmVCE_CLOCK_GATING_B, data);  in vce_v3_0_set_vce_sw_clock_gating()
191 		WREG32(mmVCE_UENC_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
196 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);  in vce_v3_0_set_vce_sw_clock_gating()
200 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
207 		WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);  in vce_v3_0_set_vce_sw_clock_gating()
212 		WREG32(mmVCE_CLOCK_GATING_B, data);  in vce_v3_0_set_vce_sw_clock_gating()
216 		WREG32(mmVCE_UENC_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
220 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);  in vce_v3_0_set_vce_sw_clock_gating()
224 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);  in vce_v3_0_set_vce_sw_clock_gating()
231 		WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);  in vce_v3_0_set_vce_sw_clock_gating()
276 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));  in vce_v3_0_start()
282 			WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));  in vce_v3_0_start()
283 			WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));  in vce_v3_0_start()
284 			WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);  in vce_v3_0_start()
285 			WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
286 			WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v3_0_start()
289 			WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));  in vce_v3_0_start()
290 			WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));  in vce_v3_0_start()
291 			WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v3_0_start()
292 			WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
293 			WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v3_0_start()
296 			WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));  in vce_v3_0_start()
297 			WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));  in vce_v3_0_start()
298 			WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);  in vce_v3_0_start()
299 			WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
300 			WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);  in vce_v3_0_start()
326 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_start()
341 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));  in vce_v3_0_stop()
352 		WREG32(mmVCE_STATUS, 0);  in vce_v3_0_stop()
355 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_stop()
537 	WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);  in vce_v3_0_mc_resume()
539 	WREG32(mmVCE_LMI_CTRL, 0x00398000);  in vce_v3_0_mc_resume()
541 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);  in vce_v3_0_mc_resume()
542 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);  in vce_v3_0_mc_resume()
543 	WREG32(mmVCE_LMI_VM_CTRL, 0);  in vce_v3_0_mc_resume()
547 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
548 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
549 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
551 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
554 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
555 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);  in vce_v3_0_mc_resume()
560 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
561 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v3_0_mc_resume()
564 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
565 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v3_0_mc_resume()
569 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);  in vce_v3_0_mc_resume()
570 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v3_0_mc_resume()
573 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);  in vce_v3_0_mc_resume()
574 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v3_0_mc_resume()
629 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_check_soft_reset()
634 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));  in vce_v3_0_check_soft_reset()
639 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));  in vce_v3_0_check_soft_reset()
666 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vce_v3_0_soft_reset()
672 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vce_v3_0_soft_reset()
760 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));  in vce_v3_0_set_clockgating_state()
767 			WREG32(mmVCE_CLOCK_GATING_A, data);  in vce_v3_0_set_clockgating_state()
773 			WREG32(mmVCE_UENC_CLOCK_GATING, data);  in vce_v3_0_set_clockgating_state()
779 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);  in vce_v3_0_set_clockgating_state()