Lines Matching refs:ring
71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v7_0_ring_get_rptr() argument
73 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_get_rptr()
75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v7_0_enc_ring_get_rptr() argument
87 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_enc_ring_get_rptr()
89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v7_0_ring_get_wptr() argument
104 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_get_wptr()
106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v7_0_enc_ring_get_wptr() argument
118 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_enc_ring_get_wptr()
120 if (ring->use_doorbell) in uvd_v7_0_enc_ring_get_wptr()
121 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()
123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) in uvd_v7_0_ring_set_wptr() argument
138 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_set_wptr()
140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) in uvd_v7_0_enc_ring_set_wptr() argument
152 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_enc_ring_set_wptr()
154 if (ring->use_doorbell) { in uvd_v7_0_enc_ring_set_wptr()
156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
163 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
166 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) in uvd_v7_0_enc_ring_test_ring() argument
177 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_enc_ring_test_ring()
178 uint32_t rptr = amdgpu_ring_get_rptr(ring); in uvd_v7_0_enc_ring_test_ring()
185 r = amdgpu_ring_alloc(ring, 16); in uvd_v7_0_enc_ring_test_ring()
188 ring->me, ring->idx, r); in uvd_v7_0_enc_ring_test_ring()
191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
192 amdgpu_ring_commit(ring); in uvd_v7_0_enc_ring_test_ring()
195 if (amdgpu_ring_get_rptr(ring) != rptr) in uvd_v7_0_enc_ring_test_ring()
202 ring->me, ring->idx, i); in uvd_v7_0_enc_ring_test_ring()
205 ring->me, ring->idx); in uvd_v7_0_enc_ring_test_ring()
222 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, in uvd_v7_0_enc_get_create_msg() argument
232 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); in uvd_v7_0_enc_get_create_msg()
259 r = amdgpu_job_submit_direct(job, ring, &f); in uvd_v7_0_enc_get_create_msg()
283 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, in uvd_v7_0_enc_get_destroy_msg() argument
293 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); in uvd_v7_0_enc_get_destroy_msg()
321 r = amdgpu_job_submit_direct(job, ring, &f); in uvd_v7_0_enc_get_destroy_msg()
323 r = amdgpu_job_submit(job, &ring->adev->vce.entity, in uvd_v7_0_enc_get_destroy_msg()
344 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) in uvd_v7_0_enc_ring_test_ib() argument
349 r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL); in uvd_v7_0_enc_ring_test_ib()
351 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r); in uvd_v7_0_enc_ring_test_ib()
355 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence); in uvd_v7_0_enc_ring_test_ib()
357 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r); in uvd_v7_0_enc_ring_test_ib()
363 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me); in uvd_v7_0_enc_ring_test_ib()
366 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r); in uvd_v7_0_enc_ring_test_ib()
368 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx); in uvd_v7_0_enc_ring_test_ib()
412 struct amdgpu_ring *ring; in uvd_v7_0_sw_init() local
455 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_sw_init()
456 sprintf(ring->name, "uvd<%d>", j); in uvd_v7_0_sw_init()
457 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); in uvd_v7_0_sw_init()
463 ring = &adev->uvd.inst[j].ring_enc[i]; in uvd_v7_0_sw_init()
464 sprintf(ring->name, "uvd_enc%d<%d>", i, j); in uvd_v7_0_sw_init()
466 ring->use_doorbell = true; in uvd_v7_0_sw_init()
472 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; in uvd_v7_0_sw_init()
474 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; in uvd_v7_0_sw_init()
476 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); in uvd_v7_0_sw_init()
523 struct amdgpu_ring *ring; in uvd_v7_0_hw_init() local
537 ring = &adev->uvd.inst[j].ring; in uvd_v7_0_hw_init()
540 ring->ready = true; in uvd_v7_0_hw_init()
541 r = amdgpu_ring_test_ring(ring); in uvd_v7_0_hw_init()
543 ring->ready = false; in uvd_v7_0_hw_init()
547 r = amdgpu_ring_alloc(ring, 10); in uvd_v7_0_hw_init()
555 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
556 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
560 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
561 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
565 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
566 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
569 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
571 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
575 amdgpu_ring_write(ring, 3); in uvd_v7_0_hw_init()
577 amdgpu_ring_commit(ring); in uvd_v7_0_hw_init()
581 ring = &adev->uvd.inst[j].ring_enc[i]; in uvd_v7_0_hw_init()
582 ring->ready = true; in uvd_v7_0_hw_init()
583 r = amdgpu_ring_test_ring(ring); in uvd_v7_0_hw_init()
585 ring->ready = false; in uvd_v7_0_hw_init()
619 adev->uvd.inst[i].ring.ready = false; in uvd_v7_0_hw_fini()
767 struct amdgpu_ring *ring; in uvd_v7_0_sriov_start() local
797 ring = &adev->uvd.inst[i].ring; in uvd_v7_0_sriov_start()
798 ring->wptr = 0; in uvd_v7_0_sriov_start()
891 size = order_base_2(ring->ring_size); in uvd_v7_0_sriov_start()
896 ring = &adev->uvd.inst[i].ring_enc[0]; in uvd_v7_0_sriov_start()
897 ring->wptr = 0; in uvd_v7_0_sriov_start()
898 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); in uvd_v7_0_sriov_start()
899 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_ad… in uvd_v7_0_sriov_start()
900 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); in uvd_v7_0_sriov_start()
929 struct amdgpu_ring *ring; in uvd_v7_0_start() local
952 ring = &adev->uvd.inst[k].ring; in uvd_v7_0_start()
1058 rb_bufsz = order_base_2(ring->ring_size); in uvd_v7_0_start()
1072 (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v7_0_start()
1076 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1078 upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1083 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); in uvd_v7_0_start()
1085 lower_32_bits(ring->wptr)); in uvd_v7_0_start()
1090 ring = &adev->uvd.inst[k].ring_enc[0]; in uvd_v7_0_start()
1091 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
1092 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
1093 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v7_0_start()
1094 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1095 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); in uvd_v7_0_start()
1097 ring = &adev->uvd.inst[k].ring_enc[1]; in uvd_v7_0_start()
1098 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
1099 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
1100 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v7_0_start()
1101 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1102 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); in uvd_v7_0_start()
1152 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in uvd_v7_0_ring_emit_fence() argument
1155 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_emit_fence()
1159 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1160 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence()
1161 amdgpu_ring_write(ring, seq); in uvd_v7_0_ring_emit_fence()
1162 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1163 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1164 amdgpu_ring_write(ring, addr & 0xffffffff); in uvd_v7_0_ring_emit_fence()
1165 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1166 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1167 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v7_0_ring_emit_fence()
1168 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1169 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1170 amdgpu_ring_write(ring, 0); in uvd_v7_0_ring_emit_fence()
1172 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1173 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1174 amdgpu_ring_write(ring, 0); in uvd_v7_0_ring_emit_fence()
1175 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1176 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1177 amdgpu_ring_write(ring, 0); in uvd_v7_0_ring_emit_fence()
1178 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_fence()
1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1180 amdgpu_ring_write(ring, 2); in uvd_v7_0_ring_emit_fence()
1191 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, in uvd_v7_0_enc_ring_emit_fence() argument
1197 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); in uvd_v7_0_enc_ring_emit_fence()
1198 amdgpu_ring_write(ring, addr); in uvd_v7_0_enc_ring_emit_fence()
1199 amdgpu_ring_write(ring, upper_32_bits(addr)); in uvd_v7_0_enc_ring_emit_fence()
1200 amdgpu_ring_write(ring, seq); in uvd_v7_0_enc_ring_emit_fence()
1201 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); in uvd_v7_0_enc_ring_emit_fence()
1209 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) in uvd_v7_0_ring_emit_hdp_flush() argument
1221 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) in uvd_v7_0_ring_test_ring() argument
1223 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_test_ring()
1228 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v7_0_ring_test_ring()
1229 r = amdgpu_ring_alloc(ring, 3); in uvd_v7_0_ring_test_ring()
1232 ring->me, ring->idx, r); in uvd_v7_0_ring_test_ring()
1235 amdgpu_ring_write(ring, in uvd_v7_0_ring_test_ring()
1236 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_test_ring()
1237 amdgpu_ring_write(ring, 0xDEADBEEF); in uvd_v7_0_ring_test_ring()
1238 amdgpu_ring_commit(ring); in uvd_v7_0_ring_test_ring()
1240 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); in uvd_v7_0_ring_test_ring()
1248 ring->me, ring->idx, i); in uvd_v7_0_ring_test_ring()
1251 ring->me, ring->idx, tmp); in uvd_v7_0_ring_test_ring()
1271 if (!p->ring->me) in uvd_v7_0_ring_patch_cs_in_place()
1293 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, in uvd_v7_0_ring_emit_ib() argument
1297 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_emit_ib()
1299 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_ib()
1300 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); in uvd_v7_0_ring_emit_ib()
1301 amdgpu_ring_write(ring, vmid); in uvd_v7_0_ring_emit_ib()
1303 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_ib()
1304 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); in uvd_v7_0_ring_emit_ib()
1305 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1306 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_ib()
1307 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); in uvd_v7_0_ring_emit_ib()
1308 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1309 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_ib()
1310 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); in uvd_v7_0_ring_emit_ib()
1311 amdgpu_ring_write(ring, ib->length_dw); in uvd_v7_0_ring_emit_ib()
1322 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, in uvd_v7_0_enc_ring_emit_ib() argument
1325 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); in uvd_v7_0_enc_ring_emit_ib()
1326 amdgpu_ring_write(ring, vmid); in uvd_v7_0_enc_ring_emit_ib()
1327 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_enc_ring_emit_ib()
1328 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_enc_ring_emit_ib()
1329 amdgpu_ring_write(ring, ib->length_dw); in uvd_v7_0_enc_ring_emit_ib()
1332 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, in uvd_v7_0_ring_emit_wreg() argument
1335 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_emit_wreg()
1337 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_wreg()
1338 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_wreg()
1339 amdgpu_ring_write(ring, reg << 2); in uvd_v7_0_ring_emit_wreg()
1340 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_wreg()
1341 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_wreg()
1342 amdgpu_ring_write(ring, val); in uvd_v7_0_ring_emit_wreg()
1343 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_wreg()
1344 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_wreg()
1345 amdgpu_ring_write(ring, 8); in uvd_v7_0_ring_emit_wreg()
1348 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in uvd_v7_0_ring_emit_reg_wait() argument
1351 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_emit_reg_wait()
1353 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_reg_wait()
1354 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_reg_wait()
1355 amdgpu_ring_write(ring, reg << 2); in uvd_v7_0_ring_emit_reg_wait()
1356 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_reg_wait()
1357 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_reg_wait()
1358 amdgpu_ring_write(ring, val); in uvd_v7_0_ring_emit_reg_wait()
1359 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_reg_wait()
1360 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); in uvd_v7_0_ring_emit_reg_wait()
1361 amdgpu_ring_write(ring, mask); in uvd_v7_0_ring_emit_reg_wait()
1362 amdgpu_ring_write(ring, in uvd_v7_0_ring_emit_reg_wait()
1363 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_reg_wait()
1364 amdgpu_ring_write(ring, 12); in uvd_v7_0_ring_emit_reg_wait()
1367 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, in uvd_v7_0_ring_emit_vm_flush() argument
1370 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in uvd_v7_0_ring_emit_vm_flush()
1373 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in uvd_v7_0_ring_emit_vm_flush()
1379 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); in uvd_v7_0_ring_emit_vm_flush()
1382 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) in uvd_v7_0_ring_insert_nop() argument
1384 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_insert_nop()
1387 WARN_ON(ring->wptr % 2 || count % 2); in uvd_v7_0_ring_insert_nop()
1390 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); in uvd_v7_0_ring_insert_nop()
1391 amdgpu_ring_write(ring, 0); in uvd_v7_0_ring_insert_nop()
1395 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) in uvd_v7_0_enc_ring_insert_end() argument
1397 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_insert_end()
1400 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, in uvd_v7_0_enc_ring_emit_reg_wait() argument
1404 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); in uvd_v7_0_enc_ring_emit_reg_wait()
1405 amdgpu_ring_write(ring, reg << 2); in uvd_v7_0_enc_ring_emit_reg_wait()
1406 amdgpu_ring_write(ring, mask); in uvd_v7_0_enc_ring_emit_reg_wait()
1407 amdgpu_ring_write(ring, val); in uvd_v7_0_enc_ring_emit_reg_wait()
1410 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, in uvd_v7_0_enc_ring_emit_vm_flush() argument
1413 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in uvd_v7_0_enc_ring_emit_vm_flush()
1415 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in uvd_v7_0_enc_ring_emit_vm_flush()
1418 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, in uvd_v7_0_enc_ring_emit_vm_flush()
1422 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, in uvd_v7_0_enc_ring_emit_wreg() argument
1425 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); in uvd_v7_0_enc_ring_emit_wreg()
1426 amdgpu_ring_write(ring, reg << 2); in uvd_v7_0_enc_ring_emit_wreg()
1427 amdgpu_ring_write(ring, val); in uvd_v7_0_enc_ring_emit_wreg()
1459 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1465 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1468 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1477 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1489 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1491 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1519 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1559 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); in uvd_v7_0_process_interrupt()
1582 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1583 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1584 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1628 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1629 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1630 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1631 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1638 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1639 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1671 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1672 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1731 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1839 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; in uvd_v7_0_set_ring_funcs()
1840 adev->uvd.inst[i].ring.me = i; in uvd_v7_0_set_ring_funcs()