Lines Matching refs:uvd
93 adev->uvd.num_uvd_inst = 1; in uvd_v5_0_early_init()
108 …_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); in uvd_v5_0_sw_init()
120 ring = &adev->uvd.inst->ring; in uvd_v5_0_sw_init()
122 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); in uvd_v5_0_sw_init()
153 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_init()
213 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_fini()
262 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
264 upper_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
278 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
296 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_start()
607 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v5_0_process_interrupt()
881 adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; in uvd_v5_0_set_ring_funcs()
891 adev->uvd.inst->irq.num_types = 1; in uvd_v5_0_set_irq_funcs()
892 adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; in uvd_v5_0_set_irq_funcs()