96 	adev->uvd.num_uvd_inst = 1;  in uvd_v4_2_early_init()
111 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);  in uvd_v4_2_sw_init()
123 	ring = &adev->uvd.inst->ring;  in uvd_v4_2_sw_init()
125 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);  in uvd_v4_2_sw_init()
158 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;  in uvd_v4_2_hw_init()
216 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;  in uvd_v4_2_hw_fini()
259 	struct amdgpu_ring *ring = &adev->uvd.inst->ring;  in uvd_v4_2_start()
556 	addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;  in uvd_v4_2_mc_resume()
568 	       (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;  in uvd_v4_2_mc_resume()
573 	addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;  in uvd_v4_2_mc_resume()
577 	addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;  in uvd_v4_2_mc_resume()
684 	amdgpu_fence_process(&adev->uvd.inst->ring);  in uvd_v4_2_process_interrupt()
772 	adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;  in uvd_v4_2_set_ring_funcs()
782 	adev->uvd.inst->irq.num_types = 1;  in uvd_v4_2_set_irq_funcs()
783 	adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;  in uvd_v4_2_set_irq_funcs()