90 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v4_2_ring_set_wptr()
271 	WREG32(mmUVD_CGC_GATE, 0);  in uvd_v4_2_start()
278 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);  in uvd_v4_2_start()
288 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v4_2_start()
289 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v4_2_start()
291 	WREG32(mmUVD_LMI_CTRL, 0x203108);  in uvd_v4_2_start()
294 	WREG32(mmUVD_MPC_CNTL, tmp | 0x10);  in uvd_v4_2_start()
296 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v4_2_start()
297 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);  in uvd_v4_2_start()
298 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v4_2_start()
299 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);  in uvd_v4_2_start()
300 	WREG32(mmUVD_MPC_SET_ALU, 0);  in uvd_v4_2_start()
301 	WREG32(mmUVD_MPC_SET_MUX, 0x88);  in uvd_v4_2_start()
351 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v4_2_start()
354 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v4_2_start()
357 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v4_2_start()
361 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);  in uvd_v4_2_start()
364 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v4_2_start()
367 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v4_2_start()
389 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v4_2_stop()
432 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |  in uvd_v4_2_stop()
436 	WREG32(mmUVD_STATUS, 0);  in uvd_v4_2_stop()
485 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v4_2_ring_test_ring()
558 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);  in uvd_v4_2_mc_resume()
559 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);  in uvd_v4_2_mc_resume()
563 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);  in uvd_v4_2_mc_resume()
564 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);  in uvd_v4_2_mc_resume()
569 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);  in uvd_v4_2_mc_resume()
570 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);  in uvd_v4_2_mc_resume()
574 	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));  in uvd_v4_2_mc_resume()
578 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));  in uvd_v4_2_mc_resume()
580 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v4_2_mc_resume()
581 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v4_2_mc_resume()
582 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v4_2_mc_resume()
598 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v4_2_enable_mgcg()
607 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v4_2_enable_mgcg()
634 	WREG32(mmUVD_CGC_CTRL, tmp);  in uvd_v4_2_set_dcm()
711 				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |  in uvd_v4_2_set_powergating_state()
722 				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |  in uvd_v4_2_set_powergating_state()